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applications, or technology described is intended to suggest possible uses and may be superseded.
ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF
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document under any intellectual property rights.
PS014004-1106
Z80180
Microprocessor Unit
v
Table of Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Multiplexed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASCI Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASCI Transmit Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASCI Receive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASCI Channel Control Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASCI Channel Control Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASCI Status Register 0, 1 (STAT0, 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSIO Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSIO Transmit/Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Data Register Channel 0L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Data Register Channel 0H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Reload Register 0L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Reload Register 0H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASCI Extension Control Register Channels 0 and 1 . . . . . . . . . . . . . . . . . . . . .
ASEXT0 and ASEXT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Data Register Channel 1L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Data Register Channel 1H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Reload Register Channel 1L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Reload Register Channel 1H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Free Running Counter I/O Address = 18H . . . . . . . . . . . . . . . . . . . . . . . . .
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PS014004-1106
Electronics Design Contest
京公网安备 11010802033920号
EEWORLD
