Complete 12-Bit 1.5/3.0/10.0 MSPS
Monolithic A/D Converters
AD9221/AD9223/AD9220
FEATURES
Monolithic 12-Bit A/D Converter Product Family
Family Members Are: AD9221, AD9223, and AD9220
Flexible Sampling Rates: 1.5 MSPS, 3.0 MSPS, and
10.0 MSPS
Low Power Dissipation: 59 mW, 100 mW, and 250 mW
Single 5 V Supply
Integral Nonlinearity Error: 0.5 LSB
Differential Nonlinearity Error: 0.3 LSB
Input Referred Noise: 0.09 LSB
Complete On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Signal-to-Noise and Distortion Ratio: 70 dB
Spurious-Free Dynamic Range: 86 dB
Out-of-Range Indicator
Straight Binary Output Data
28-Lead SOIC and 28-Lead SSOP
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
CLK
SHA
VINA
VINB
MDAC1
GAIN = 16
A/D
MDAC2
GAIN = 8
A/D
MDAC3
GAIN = 4
A/D
AVDD
DVDD
5
4
3
A/D
CAPT
CAPB
VREF
SENSE
MODE
SELECT
5
4
3
DIGITAL CORRECTION LOGIC
12
OUTPUT BUFFERS
1V
3
OTR
BIT 1
(MSB)
BIT 12
(LSB)
AD9221/AD9223/AD9220
REFCOM
AVSS
DVSS
CML
The AD9221, AD9223, and AD9220 are a generation of high
performance, single supply 12-bit analog-to-digital converters.
Each device exhibits true 12-bit linearity and temperature drift
performance
1
as well as 11.5-bit or better ac performance.
2
The
AD9221/AD9223/AD9220 share the same interface options,
package, and pinout. Thus, the product family provides an upward
or downward component selection path based on performance,
sample rate and power. The devices differ with respect to their
specified sampling rate, and power consumption, which is reflected
in their dynamic performance over frequency.
The AD9221/AD9223/AD9220 combine a low cost, high speed
CMOS process and a novel architecture to achieve the resolution
and speed of existing hybrid and monolithic implementations at
a fraction of the power consumption and cost. Each device is a
complete, monolithic ADC with an on-chip, high performance,
low noise sample-and-hold amplifier and programmable voltage
reference. An external reference can also be chosen to suit the
dc accuracy and temperature drift requirements of the application.
The devices use a multistage differential pipelined architecture
with digital output error correction logic to provide 12-bit accu-
racy at the specified data rates and to guarantee no missing
codes over the full operating temperature range.
The input of the AD9221/AD9223/AD9220 is highly flexible,
allowing for easy interfacing to imaging, communications, medi-
cal, and data-acquisition systems. A truly differential input
structure allows for both single-ended and differential input
interfaces of varying input spans. The sample-and-hold
NOTES
1
Excluding internal voltage reference.
2
Depends on the analog input configuration.
amplifier (SHA) is equally suited for both multiplexed sys-
tems that switch full-scale voltage levels in successive channels
as well as sampling single-channel inputs at frequencies up to
and beyond the Nyquist rate. Also, the AD9221/AD9223/AD9220
is well suited for communication systems employing Direct-
IF down conversion since the SHA in the differential input
mode can achieve excellent dynamic performance
far beyond
its
specified Nyquist frequency.
2
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range (OTR) signal indicates an over-
flow condition that can be used with the most significant bit to
determine low or high overflow.
PRODUCT HIGHLIGHTS
The AD9221/AD9223/AD9220 family offers a complete single-
chip sampling 12-bit, analog-to-digital conversion function in
pin compatible 28-lead SOIC and SSOP packages.
Flexible Sampling Rates—The AD9221, AD9223, and AD9220
offer sampling rates of 1.5 MSPS, 3.0 MSPS, and 10.0 MSPS,
respectively.
Low Power and Single Supply—The AD9221, AD9223, and
AD9220 consume only 59 mW, 100 mW, and 250 mW, respec-
tively, on a single 5 V power supply.
Excellent DC Performance Over Temperature—The AD9221/
AD9223/AD9220 provide 12-bit linearity and temperature drift
performance.
1
Excellent AC Performance and Low Noise—The AD9221/
AD9223/AD9220 provide better than 11.3 ENOB performance
and have an input referred noise of 0.09 LSB rms.
2
Flexible Analog Input Range—The versatile on-board sample-
and-hold (SHA) can be configured for either single-ended or
differential inputs of varying input spans.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD9221/AD9223/AD9220–SPECIFICATIONS
DC SPECIFICATIONS
Parameter
RESOLUTION
MAX CONVERSION RATE
INPUT REFERRED NOISE (TYP)
V
REF
= 1 V
V
REF
= 2.5 V
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
INL
1
DNL
1
No Missing Codes
Zero Error (@ 25°C)
Gain Error (@ 25°C)
2
Gain Error (@ 25°C)
3
TEMPERATURE DRIFT
Zero Error
Gain Error
2
Gain Error
3
POWER SUPPLY REJECTION
AVDD, DVDD (+5 V
±
0.25 V)
ANALOG INPUT
Input Span (with V
REF
= 1.0 V)
Input Span (with V
REF
= 2.5 V)
Input (VINA or VINB) Range
Input Capacitance
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Output Voltage Tolerance (1 V Mode)
Output Voltage (2.5 V Mode)
Output Voltage Tolerance (2.5 V Mode)
Load Regulation
4
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltages
AVDD
DVDD
Supply Current
IAVDD
IDVDD
POWER CONSUMPTION
(AVDD = 5 V, DVDD = 5 V, f
SAMPLE
= Max Conversion Rate, V
REF
= 2.5 V, VINB = 2.5 V, T
MIN
to T
MAX
, unless
otherwise noted.)
AD9221
12
1.5
0.23
0.09
±
0.4
±
1.25
±
0.3
±
0.75
±
0.6
±
0.3
12
±
0.3
±
1.5
±
0.75
±
2
±
26
±
0.4
±
0.06
2
5
0
AVDD
16
1
±
14
2.5
±
35
2.0
5
AD9223
12
3
0.23
0.09
±
0.5
±
1.25
±
0.3
±
0.75
±
0.6
±
0.3
12
±
0.3
±
1.5
±
0.75
±
2
±
26
±
0.4
±
0.06
2
5
0
AVDD
16
1
±
14
2.5
±
35
2.0
5
AD9220
12
10
0.23
0.09
±
0.5
±
1.25
±
0.3
±
0.75
±
0.7
±
0.35
12
±
0.3
±
1.5
±
0.75
±
2
±
26
±
0.4
±
0.06
2
5
0
AVDD
16
1
±
14
2.5
±
35
2.0
5
Unit
Bits min
MHz min
LSB rms typ
LSB rms typ
LSB typ
LSB max
LSB typ
LSB max
LSB typ
LSB typ
Bits Guaranteed
% FSR max
% FSR max
% FSR max
ppm/°C typ
ppm/°C typ
ppm/°C typ
% FSR max
V p-p min
V p-p max
V min
V max
pF typ
V typ
mV max
V typ
mV max
mV max
kΩ typ
5
2.7 to 5.25
14.0
11.8
0.5
0.02
59.0
70.0
5
2.7 to 5.25
26
20
0.5
0.02
100
130
5
2.7 to 5.25
58
51
4.0
<1.0
254
310
V (± 5% AVDD Operating)
V
mA max
mA typ
mA max
mA typ
mW typ
mW max
NOTES
1
V
REF
= 1 V.
2
Including internal reference.
3
Excluding internal reference.
4
Load regulation with 1 mA load current (in addition to that required by the AD9221/AD9223/AD9220).
Specification subject to change without notice.
–2–
REV. E
AD9221/AD9223/AD9220
AC SPECIFICATIONS
Parameter
MAX CONVERSION RATE
DYNAMIC PERFORMANCE
Input Test Frequency 1 (VINA = –0.5 dBFS)
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOBs)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious Free Dynamic Range (SFDR)
Input Test Frequency 2 (VINA = –0.5 dBFS)
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOBs)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious Free Dynamic Range (SFDR)
Full Power Bandwidth
Small Signal Bandwidth
Aperture Delay
Aperture Jitter
Acquisition to Full-Scale Step
Specifications subject to change without notice.
(AVDD = 5 V, DVDD= 5 V, f
SAMPLE
= Max Conversion Rate, V
REF
= 1.0 V, VINB = 2.5 V, DC Coupled/Single-
Ended Input T
MIN
to T
MAX
, unless otherwise noted.)
AD9221
1.5
100
70.0
69.0
11.3
11.2
70.2
69.0
–83.4
–77.5
86.0
79.0
0.50
69.9
69.0
11.3
11.2
70.1
69.0
–83.4
–77.5
86.0
79.0
25
25
1
4
125
AD9223
3.0
500
70.0
68.5
11.3
11.1
70.0
68.5
–83.4
–76.0
87.5
77.5
1.50
69.4
68.0
11.2
11.1
69.7
68.5
–82.9
–75.0
85.7
76.0
40
40
1
4
43
AD9220
10.0
1000
70
68.5
11.3
11.1
70.2
69.0
–83.7
–76.0
88.0
77.5
5.0
67.0
65.0
10.8
10.5
68.8
67.5
–72.0
–68.0
75.0
69.0
60
60
1
4
30
Unit
MHz min
kHz
dB typ
dB min
dB typ
dB min
dB typ
dB min
dB typ
dB max
dB typ
dB max
MHz
dB typ
dB min
dB typ
dB min
dB typ
dB min
dB typ
dB max
dB typ
dB max
MHz typ
MHz typ
ns typ
ps rms typ
ns typ
DIGITAL SPECIFICATIONS
Parameter
(AVDD = 5 V, DVDD = 5 V, T
MIN
to T
MAX
, unless otherwise noted.)
Symbol
V
IH
V
IL
I
IH
I
IL
C
IN
3.5
1.0
±
10
±
10
5
Unit
V min
V max
µA
max
µA
max
pF typ
CLOCK INPUT
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (V
IN
= DVDD)
Low Level Input Current (V
IN
= 0 V)
Input Capacitance
LOGIC OUTPUTS
DVDD = 5 V
High Level Output Voltage (I
OH
= 50
µA)
High Level Output Voltage (I
OH
= 0.5 mA)
Low Level Output Voltage (I
OL
= 1.6 mA)
Low Level Output Voltage (I
OL
= 50
µA)
DVDD = 3 V
High Level Output Voltage (I
OH
= 50
µA)
High Level Output Voltage (I
OH
= 0.5 mA)
Low Level Output Voltage (I
OL
= 1.6 mA)
Low Level Output Voltage (I
OL
= 50
µA)
Output Capacitance
Specifications subject to change without notice.
V
OH
V
OH
V
OL
V
OL
V
OH
V
OH
V
OL
V
OL
C
OUT
4.5
2.4
0.4
0.1
2.95
2.80
0.4
0.05
5
V min
V min
V max
V max
V min
V min
V max
V max
pF typ
REV. E
–3–
AD9221/AD9223/AD9220
SWITCHING SPECIFICATIONS
Parameter
Clock Period*
CLOCK Pulsewidth High
CLOCK Pulsewidth Low
Output Delay
(T
MIN
to T
MAX
with AVDD = 5 V, DVDD = 5 V, C
L
= 20 pF)
AD9221
667
300
300
8
13
19
3
AD9223
333
150
150
8
13
19
3
AD9220
100
45
45
8
13
19
3
Unit
ns min
ns min
ns min
ns min
ns typ
ns max
Clock Cycles
Symbol
t
C
t
CH
t
CL
t
OD
Pipeline Delay (Latency)
Specifications subject to change without notice.
*The
clock period may be extended to 1 ms without degradation in specified performance @ 25
°C.
S1
ANALOG
INPUT
S2
t
C
t
CH
t
CL
S4
S3
INPUT
CLOCK
t
OD
DATA
OUTPUT
DATA 1
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
THERMAL CHARACTERISTICS
Parameter
AVDD
DVDD
AVSS
AVDD
REFCOM
CLK
Digital Outputs
VINA, VINB
VREF
SENSE
CAPB, CAPT
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)
With
Respect
to
AVSS
DVSS
DVSS
DVDD
AVSS
AVSS
DVSS
AVSS
AVSS
AVSS
AVSS
Min
–0.3
–0.3
–0.3
–6.5
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–65
Max
+6.5
+6.5
+0.3
+6.5
+0.3
AVDD + 0.3
DVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
150
+150
300
Unit
V
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
Thermal Resistance
28-Lead SOIC
JA
= 71.4°C/W
JC
= 23°C/W
28-Lead SSOP
JA
= 63.3°C/W
JC
= 23°C/W
ORDERING GUIDE
Model
AD9221AR
AD9223AR
AD9220AR
AD9221ARS
AD9223ARS
AD9220ARS
AD9221-EB
AD9223-EB
AD9220-EB
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package
Description
28-Lead SOIC
28-Lead SOIC
28-Lead SOIC
28-Lead SSOP
28-Lead SSOP
28-Lead SSOP
Evaluation Board
Evaluation Board
Evaluation Board
Package
Option
R-28
R-28
R-28
RS-28
RS-28
RS-28
*Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9221/AD9223/AD9220 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
–4–
REV. E
AD9221/AD9223/AD9220
PIN CONFIGURATION
CLK 1
(LSB) BIT 12 2
BIT 11 3
BIT 10 4
BIT 9 5
BIT 8 6
BIT 7 7
28 DVDD
27 DVSS
26 AVDD
Zero Error
The major carry transition should occur for an analog value 1/2
LSB below VINA = VINB. Zero error is defined as the devia-
tion of the actual transition from that point.
Gain Error
AD9221/
AD9223/
AD9220
25 AVSS
24 VINB
23 VINA
TOP VIEW 22 CML
8 (Not to Scale) 21 CAPT
BIT 6
BIT 5 9
BIT 4 10
BIT 3 11
BIT 2 12
(MSB) BIT 1 13
OTR 14
20 CAPB
19 REFCOM
18 VREF
17 SENSE
16 AVSS
15 AVDD
The first code transition should occur at an analog value 1/2 LSB
above negative full scale. The last transition should occur at an
analog value 1 1/2 LSB below the nominal full scale. Gain error
is the deviation of the actual difference between first and last
code transitions and the ideal difference between first and last
code transitions.
Temperature Drift
The temperature drift for zero error and gain error specifies the
maximum change from the initial (25°C) value to the value at
T
MIN
or T
MAX
.
Power Supply Rejection
PIN FUNCTION DESCRIPTIONS
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value with
the supply at its maximum limit.
Aperture Jitter
Pin
Number
1
2
3–12
13
14
15, 26
16, 25
17
18
19
20
21
22
23
24
27
28
Mnemonic
CLK
BIT 12
BITS 11–2
BIT 1
OTR
AVDD
AVSS
SENSE
VREF
REFCOM
CAPB
CAPT
CML
VINA
VINB
DVSS
DVDD
Description
Clock Input Pin
Least Significant Data Bit (LSB)
Data Output Bit
Most Significant Data Bit (MSB)
Out of Range
5 V Analog Supply
Analog Ground
Reference Select
Reference I/O
Reference Common
Noise Reduction Pin
Noise Reduction Pin
Common-Mode Level (Midsupply)
Analog Input Pin (+)
Analog Input Pin (–)
Digital Ground
3 V to 5 V Digital Supply
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
Aperture Delay
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
S/N+D is expressed in decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
N
=
(
SINAD
– 1.76
)
/ 6.02
it is possible to get a measure of performance expressed as
N,
the effective number of bits.
Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.
Total Harmonic Distortion (THD)
DEFINITIONS OF SPECIFICATIONS
Integral Nonlinearity (INL)
INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as negative full scale occurs 1/2 LSB before the
first code transition. Positive full scale is defined as a level 1 1/2
LSB beyond the last code transition. The deviation is measured
from the middle of each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
Signal-to-Noise Ratio (SNR)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096
codes, respectively, must be present over all operating ranges.
SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
REV. E
–5–
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