19-2442; Rev 4; 5/09
KIT
ATION
EVALU
E
BL
AVAILA
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel 2-Wire Serial 8-Bit ADCs
General Description
The MAX1036–MAX1039 low-power, 8-bit, multichannel,
analog-to-digital converters (ADCs) feature internal
track/hold (T/H), voltage reference, clock, and an
I
2
C-compatible 2-wire serial interface. These devices
operate from a single supply and require only 350µA at
the maximum sampling rate of 188ksps. Auto-
Shutdown™ powers down the devices between conver-
sions reducing supply current to less than 1µA at low
throughput rates. The MAX1036/MAX1037 have four ana-
log input channels each, while the MAX1038/MAX1039
have twelve analog input channels. The analog inputs are
software configurable for unipolar or bipolar and single-
ended or pseudo-differential operation.
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to V
DD
. The MAX1037/
MAX1039 feature a 2.048V internal reference and the
MAX1036/MAX1038 feature a 4.096V internal reference.
The MAX1036/MAX1037 are available in 8-pin SOT23
packages. The MAX1038/MAX1039 are available in 16-
pin QSOP packages. The MAX1036–MAX1039 are guar-
anteed over the extended industrial temperature range
(-40°C to +85°C). Refer to MAX1136–MAX1139 for 10-bit
devices and to the MAX1236–MAX1239 for 12-bit
devices.
Features
o
High-Speed I
2
C-Compatible Serial Interface
400kHz Fast Mode
1.7MHz High-Speed Mode
o
Single Supply
2.7V to 3.6V (MAX1037/MAX1039)
4.5V to 5.5V (MAX1036/MAX1038)
o
Internal Reference
2.048V (MAX1037/MAX1039)
4.096V (MAX1036/MAX1038)
o
External Reference: 1V to V
DD
o
Internal Clock
o
4-Channel Single-Ended or 2-Channel Pseudo-
Differential (MAX1036/MAX1037)
o
12-Channel Single-Ended or 6-Channel Pseudo-
Differential (MAX1038/MAX1039)
o
Internal FIFO with Channel-Scan Mode
o
Low Power
350µA at 188ksps
110µA at 75ksps
8µA at 10ksps
1µA in Power-Down Mode
o
Software Configurable Unipolar/Bipolar
o
Small Packages
8-Pin SOT23 (MAX1036/MAX1037)
16-Pin QSOP (MAX1038/MAX1039)
Pin Configurations and Typical Operating Circuit appear
at end of data sheet.
MAX1036–MAX1039
Applications
Handheld Portable Applications
Medical Instruments
Battery-Powered Test Equipment
Solar-Powered Remote Systems
Received-Signal-Strength Indicators
System Supervision
Ordering Information/Selector Guide
PART
MAX1036EKA+T
MAX1037EKA+T
MAX1038AEEE+
MAX1039AEEE+
PIN-PACKAGE
8 SOT23
8 SOT23
16 QSOP
16 QSOP
TUE
(LSB)
±2
±2
±1
±1
INPUT
CHANNELS
4
4
12
12
I
2
C
SLAVE ADDRESS
1100100
1100100
1100101
1100101
INTERNAL
REFERENCE (V)
4.096
2.048
4.096
2.048
TOP MARK
AAJE
AAJG
—
—
+Denotes
a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel 2-Wire Serial 8-Bit ADCs
MAX1036–MAX1039
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND ..............................................................-0.3V to +6V
AIN0–AIN11, REF to
GND ......................-0.3V to the lower of (V
DD
+ 0.3V) and +6V
SDA, SCL to GND.....................................................-0.3V to +6V
Maximum Current Into Any Pin .........................................±50mA
Continuous Power Dissipation (T
A
= +70°C)
8-Pin SOT23 (derate 7.1mW/°C above +70°C).............567mW
16-Pin QSOP (derate 8.3mW/°C above +70°C).........666.7mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 2.7V to 3.6V (MAX1037/MAX1039), V
DD
= 4.5V to 5.5V (MAX1036/MAX1038). External reference, V
REF
= 2.048V
(MAX1037/MAX1039), V
REF
= 4.096V (MAX1036/MAX1038). External clock, f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless otherwise
noted. Typical values are at T
A
= +25°C.)
PARAMETER
DC ACCURACY
(Note 1)
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Offset Error Temperature
Coefficient
Gain Error
Gain Temperature Coefficient
Total Unadjusted Error
Channel-to-Channel Offset
Matching
Channel-to-Channel Gain
Matching
Input Common-Mode Rejection
Ratio
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
Full-Power Bandwidth
Full-Linear Bandwidth
CONVERSION RATE
Conversion Time (Note 5)
t
CONV
Internal clock
External clock
4.7
6.1
µs
CMRR
Pseudo-differential input mode
TUE
MAX1036/MAX1037
MAX1038A/MAX1039A
(Note 3)
±1
±0.5
±0.5
±0.1
±0.5
75
±2
±1
3
±1
INL
DNL
(Note 2)
No missing codes over temperature
8
±1
±1
±1.5
Bits
LSB
LSB
LSB
ppm/°C
LSB
ppm/°C
LSB
LSB
LSB
dB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE
(f
IN(sine wave)
= 25kHz, V
IN
= V
REF(P-P)
, f
SAMPLE
= 188ksps, R
IN
= 100Ω)
SINAD
THD
SFDR
(Note 4)
-3dB point
SINAD > 49dB
Up to the 5th harmonic
49
-69
69
75
2.0
200
dB
dB
dB
dB
MHz
kHz
2
_______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel 2-Wire Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 3.6V (MAX1037/MAX1039), V
DD
= 4.5V to 5.5V (MAX1036/MAX1038). External reference, V
REF
= 2.048V
(MAX1037/MAX1039), V
REF
= 4.096V (MAX1036/MAX1038). External clock, f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless otherwise
noted. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
Internal clock, SCAN[1:0] = 01
(MAX1036/MAX1037)
Throughput Rate
f
SAMPLE
Internal clock, SCAN[1:0] = 00
CS[3:0] = 1011 (MAX1038/MAX1039)
External clock
Track/Hold Acquisition Time
Internal Clock Frequency
Aperture Delay
ANALOG INPUT (AIN0–AIN11)
Input Voltage Range, Single
Ended and Differential (Note 6)
Input Multiplexer Leakage Current
Input Capacitance
INTERNAL REFERENCE
(Note 7)
Reference Voltage
Reference Temperature
Coefficient
Reference Short-Circuit Current
Reference Source Impedance
EXTERNAL REFERENCE
Reference Input Voltage Range
REF Input Current
Input High Voltage
Input Low Voltage
Input Hysteresis
Input Current
Input Capacitance
Output Low Voltage
V
REF
I
REF
V
IH
V
IL
V
HYST
I
IN
C
IN
V
OL
I
SINK
= 3mA
V
IN
= 0 to V
DD
15
0.4
0.1 x V
DD
±10
(Note 9)
f
SAMPLE
= 188ksps
0.7 x V
DD
0.3 x V
DD
1.0
14
V
DD
30
V
µA
V
V
V
µA
pF
V
(Note 8)
675
V
REF
TC
REF
T
A
= +25°C
MAX1037/MAX1039
MAX1036/MAX1038
1.925
3.850
2.048
4.096
120
10
2.171
4.342
V
ppm/°C
mA
Ω
C
IN
Unipolar
Bipolar
On/off-leakage current, V
AIN
_= 0 or V
DD,
no clock, f
SCL
= 0
±0.01
18
0
V
REF
±V
REF
/ 2
±1
V
µA
pF
t
AD
External clock, fast mode
External clock, high-speed mode
588
2.25
45
30
MIN
TYP
MAX
76
77
188
ns
MHz
ns
ksps
UNITS
MAX1036–MAX1039
DIGITAL INPUTS/OUTPUTS (SCL, SDA)
_______________________________________________________________________________________
3
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel 2-Wire Serial 8-Bit ADCs
MAX1036–MAX1039
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 3.6V (MAX1037/MAX1039), V
DD
= 4.5V to 5.5V (MAX1036/MAX1038). External reference, V
REF
= 2.048V
(MAX1037/MAX1039), V
REF
= 4.096V (MAX1036/MAX1038). External clock, f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless otherwise
noted. Typical values are at T
A
= +25°C.)
PARAMETER
POWER REQUIREMENTS
Supply Voltage (Note 10)
V
DD
MAX1037/MAX1039
MAX1036/MAX1038
f
SAMPLE
=
188ksps
f
SAMPLE
=
75ksps
Supply Current
I
DD
f
SAMPLE
=
10ksps
f
SAMPLE
=
1ksps
Power-down
Power-Supply Rejection Ratio
Serial Clock Frequency
Bus Free Time Between a STOP
and a START Condition
Hold Time for Start Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated START
Condition (Sr)
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of SDA Transmitting
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
Serial Clock Frequency
Hold Time (Repeated) Start
Condition
Low Period of the SCL Clock
High Period of the SCL Clock
PSRR
f
SCL
t
BUF
t
HD, STA
t
LOW
t
HIGH
t
SU, STA
t
HD, DAT
t
SU, DAT
t
R
t
F
t
SU, STO
C
B
t
SP
f
SCLH
t
HD, STA
t
LOW
t
HIGH
(Note 14)
160
320
120
(Note 13)
(Note 13)
(Note 12)
1.3
0.6
1.3
0.6
0.6
0
100
20 + 0.1C
B
20 + 0.1C
B
0.6
400
50
1.7
300
300
150
(Note 11)
TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE
(Figures 1A and 2)
400
kHz
µs
µs
µs
µs
µs
ns
ns
ns
ns
µs
pF
ns
MHz
ns
ns
ns
Internal REF, external clock
External REF, external clock
External REF, external clock
External REF, internal clock
External REF, external clock
External REF, internal clock
External REF, external clock
External REF, internal clock
2.7
4.5
350
250
110
150
8
10
2
2.5
1
±0.25
10
±1
LSB/V
µA
3.6
5.5
650
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE
(Figures 1B and 2)
4
_______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel 2-Wire Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 3.6V (MAX1037/MAX1039), V
DD
= 4.5V to 5.5V (MAX1036/MAX1038). External reference, V
REF
= 2.048V
(MAX1037/MAX1039), V
REF
= 4.096V (MAX1036/MAX1038). External clock, f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless otherwise
noted. Typical values are at T
A
= +25°C.)
PARAMETER
Setup Time for a Repeated START
Condition (Sr)
Data Hold Time
Data Setup Time
Rise Time of SCL Signal
(Current Source Enabled)
Rise Time of SCL Signal After
Acknowledge Bit
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
SYMBOL
t
SU
,
STA
t
HD
,
DAT
t
SU
,
DAT
t
RCL
t
RCL1
t
FCL
t
RDA
t
FDA
t
SU
,
STO
C
B
t
SP
0
(Note 13)
(Note 13)
(Note 13)
(Note 13)
(Note 13)
(Note 12)
CONDITIONS
MIN
160
0
10
20
20
20
20
20
160
400
10
80
160
80
160
160
150
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
ns
MAX1036–MAX1039
Note 1:
The MAX1036/MAX1038 are tested at V
DD
= 5V and the MAX1037/MAX1039 are tested at V
DD
= 3V. All devices are config-
ured for unipolar, single-ended inputs.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 3:
Offset nulled.
Note 4:
Ground on channel; sine wave applied to all off channels.
Note 5:
Conversion time is defined as the number of clock cycles (8) multiplied by the clock period. Conversion time does not
include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6:
The absolute voltage range for the analog inputs (AIN0–AIN11) is from GND to V
DD
.
Note 7:
When AIN_/REF is configured to be an internal reference (SEL[2:1] = 11), decouple AIN_/REF to GND with a 0.01µF capacitor.
Note 8:
The switch connecting the reference buffer to AIN_/REF has a typical on-resistance of 675Ω.
Note 9:
ADC performance is limited by the converter’s noise floor, typically 1.4mV
P-P
.
Note 10:
Electrical characteristics are guaranteed from V
DD(min)
to V
DD(max)
. For operation beyond this range, see the
Typical
Operating Characteristics.
Note 11:
Power-supply rejection ratio is measured as:
[
V
FS
(
3.3V
)
−
V
FS
(
2.7V
)
×
3.3V
−
2.7V
]
2
N
V
REF
, for the MAX1037/MAX1039 where N is the number of bits and V
REF
= 2.048V.
Power-supply rejection ratio is measured as:
[
V
FS
(
5.5V
)
−
V
FS
(
4.5V
)
]
×
V2
REF
, for the MAX1036/MAX1038 where N is the number of bits and V
REF
= 4.096V.
Note 12:
A master device must provide a data hold time for SDA (referred to V
IL
of SCL) in order to bridge the undefined region of
SCL’s falling edge (Figure 1).
Note 13:
C
B
= total capacitance of one bus line in pF. t
R
, t
FDA
, and t
F
measured between 0.3V
DD
and 0.7V
DD
. The minimum value is
specified at +25°C with C
B
= 400pF.
Note 14:
f
SCLH
must meet the minimum clock low time plus the rise/fall times.
_______________________________________________________________________________________
5
5.5V
−
4.5V
N
京公网安备 11010802033920号
EEWORLD
