82V3012PVG datasheet, PDF - EEWORLD Datasheet

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82V3012PVG: DescriptionClock Generators u0026 Support Products 3.3V T1/E1/19.44M Stratum dual ref WAN; Categorysemiconductor Analog mixed-signal IC; File Size415KB，32 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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Clock Generators u0026 Support Products 3.3V T1/E1/19.44M Stratum dual ref WAN

82V3012PVG Parametric

Parameter Name	Attribute value
Product Category	Clock Generators & Support Products
Manufacturer	IDT (Integrated Device Technology, Inc.)
RoHS	Details
Maximum Input Frequency	19 MHz
Maximum Operating Temperature	+ 85 C
Minimum Operating Temperature	- 40 C
Mounting Style	SMD/SMT
Package / Case	SSOP-56
Packaging	Tube
Height	2.3 mm
Length	18.4 mm
Factory Pack Quantity	26
Supply Voltage - Max	3.6 V
Supply Voltage - Min	3 V
Width	7.5 mm
Unit Weight	0.024508 oz

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T1/E1/OC3 WAN PLL WITH DUAL

REFERENCE INPUTS

FEATURES

• Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum

3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces

• Supports ITU-T G.813 Option 1 clocks

• Supports ITU-T G.812 Type IV clocks

• Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing

for E1 interface

• Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or

19.44 MHz

• Accepts two independent reference inputs which may have

same or different nominal frequencies applied to them

• Provides C1.5o,

C3o,

C2o,

C4o,

C6o, C8o,

C16o,

C19o and

C32o

output clock signals

• Provides 7 types of 8 kHz framing pulses:

F0o,

F8o,

F16o,

F19o,

F32o,

RSP and TSP

IDT82V3012

• Provides a C2/C1.5 output clock signal with the frequency

controlled by the selected reference input Fref0 or Fref1

• Holdover frequency accuracy of 0.025 ppm

• Phase slope of 5 ns per 125 µs

• Attenuates wander from 2.1 Hz

• Fast lock mode

• Provides Time Interval Error (TIE) correction

• MTIE of 600 ns

• JTAG boundary scan

• Holdover status indication

• Freerun status indication

• Normal status indication

• Lock status indication

• Input reference quality indication

• 3.3 V operation with 5 V tolerant I/O

• Package available: 56-pin SSOP (Green option available)

FUNCTIONAL BLOCK DIAGRAM

TDO

TDI

OSCi

TCLR

RST

DDD

DDA

C2/C1.5

TCK

TMS

TRST

Fref0

Fref1

IN_sel

FLOCK

DPLL

JTAG

OSC

C32o

C19o

C19POS

C19NEG

TIE Control

Block

Virtual

Reference

Reference Input

Switch

C16o

C8o

C4o

C2o

C3o

C1.5o

C6o

F0o

F8o

F16o

F19o

F32o

RSP

TSP

LOCK

Frequency

Select Circuit 0

MON_out0

Reference Input

Monitor 0

Reference Input

Monitor 1

Feedback Signal

MON_out1

Invalid Input

Signal Detection

F0_sel0

F0_sel1

State Control Circuit

Frequency

Select Circuit 1

F1_sel0

F1_sel1

TIE_en MODE_sel1 MODE_sel0 Normal Holdover Freerun

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.

2006

Integrated Device Technology, Inc.

February 6, 2009

DSC-6238/6

TABLE OF CONTENTS

Pin Description...................................................................................................................................................................................................7

Functional Description ....................................................................................................................................................................................10

2.1 State Control Circuit ................................................................................................................................................................................10

2.1.1 Normal Mode..............................................................................................................................................................................11

2.1.2 Fast Lock Mode..........................................................................................................................................................................11

2.1.3 Holdover Mode ...........................................................................................................................................................................11

2.1.4 Freerun Mode.............................................................................................................................................................................11

2.2 Frequency Select Circuit .........................................................................................................................................................................11

2.3 Reference Input Switch ...........................................................................................................................................................................11

2.4 Reference Input Monitor ..........................................................................................................................................................................12

2.5 Invalid Input Signal Detection ..................................................................................................................................................................12

2.6 TIE Control Block.....................................................................................................................................................................................12

2.7 DPLL Block..............................................................................................................................................................................................13

2.7.1 Phase Detector (PHD)................................................................................................................................................................13

2.7.2 Limiter.........................................................................................................................................................................................13

2.7.3 Loop Filter ..................................................................................................................................................................................14

2.7.4 Fraction Block.............................................................................................................................................................................14

2.7.5 Digital Control Oscillator (DCO)..................................................................................................................................................14

2.7.6 Lock Indicator .............................................................................................................................................................................14

2.7.7 Output Interface..........................................................................................................................................................................14

2.8 OSC.........................................................................................................................................................................................................15

2.8.1 Clock Oscillator ..........................................................................................................................................................................15

2.9 JTAG .......................................................................................................................................................................................................15

2.10 Reset, Lock and TIE Application .............................................................................................................................................................15

2.11 Power Supply Filtering Techniques .........................................................................................................................................................16

Measures of Performance ...............................................................................................................................................................................17

3.1 Intrinsic Jitter ...........................................................................................................................................................................................17

3.2 Jitter Tolerance........................................................................................................................................................................................17

3.3 Jitter Transfer ..........................................................................................................................................................................................17

3.4 Frequency Accuracy................................................................................................................................................................................17

3.5 Holdover Accuracy ..................................................................................................................................................................................17

3.6 Capture Range ........................................................................................................................................................................................17

3.7 Lock Range .............................................................................................................................................................................................17

3.8 Phase Slope ............................................................................................................................................................................................17

3.9 Time Interval Error (TIE)..........................................................................................................................................................................17

3.10 Maximum Time Interval Error (MTIE) ......................................................................................................................................................17

3.11 Phase Continuity .....................................................................................................................................................................................18

3.12 Phase Lock Time.....................................................................................................................................................................................18

Absolute Maximum Ratings ............................................................................................................................................................................19

Recommended DC Operating Conditions .....................................................................................................................................................19

DC Electrical Characteristics ..........................................................................................................................................................................19

6.1 Single End Input/Output Port...................................................................................................................................................................19

6.2 Differential Output Port (LVDS) ...............................................................................................................................................................20

AC Electrical Characteristics .........................................................................................................................................................................21

7.1 Performance ............................................................................................................................................................................................21

7.2 Intrinsic Jitter Unfiltered ...........................................................................................................................................................................22

7.3 C1.5o (1.544 MHz) Intrinsic Jitter Filtered ...............................................................................................................................................22

7.4 C2o (2.048 MHz) Intrinsic Jitter Filtered ..................................................................................................................................................22

7.5 C19o (19.44 MHz) Intrinsic Jitter Filtered ................................................................................................................................................22

7.6 8 kHz Input to 8 kHz Output Jitter Transfer .............................................................................................................................................23

7.7 1.544 MHz Input to 1.544 MHz Output Jitter Transfer.............................................................................................................................23

7.8 2.048 MHz Input to 2.048 MHz Output Jitter Transfer.............................................................................................................................23

February 6, 2009

Table Of Contents

LIST OF FIGURES

Figure - 1

Figure - 2

Figure - 3

Figure - 4

Figure - 5

Figure - 6

Figure - 7

Figure - 8

Figure - 9

Figure - 10

Figure - 11

Figure - 12

Figure - 13

Figure - 14

Figure - 15

IDT82V3012 SSOP56 Package Pin Assignment ................................................................................................................................ 2

State Control Circuit .......................................................................................................................................................................... 10

State Control Diagram....................................................................................................................................................................... 10

TIE Control Block Diagram................................................................................................................................................................ 12

Reference Switch with TIE Control Block Enabled............................................................................................................................ 13

Reference Switch with TIE Control Block Disabled........................................................................................................................... 13

DPLL Block Diagram ......................................................................................................................................................................... 14

Clock Oscillator Circuit ...................................................................................................................................................................... 15

Power-Up Reset Circuit..................................................................................................................................................................... 16

IDT82V3012 Power Decoupling Scheme.......................................................................................................................................... 16

Timing Parameter Measurement Voltage Levels .............................................................................................................................. 27

Input to Output Timing (Normal Mode).............................................................................................................................................. 29

Output Timing 1................................................................................................................................................................................. 30

Output Timing 2................................................................................................................................................................................. 31

Input Control Setup and Hold Timing ................................................................................................................................................ 31

List of Figures

February 6, 2009

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