FemtoClock
®
Crystal-To-3.3V LVPECL
Frequency Synthesizers
843242
DATASHEET
General Description
The 843242 is a two differential output LVPECL Synthesizer
designed to generate Ethernet reference clock frequencies. Using a
31.25MHz or 26.041666MHz, 18pF parallel resonant crystal, the
following frequencies can be generated based on the settings of 4
frequency select pins (SELA[1:0], SELB[1:0]): 625MHz, 312.5MHz,
156.25MHz, and 125MHz.
The two banks have their own dedicated frequency select pins and
can be independently set for the frequencies mentioned above. The
843242 IDT’s 3
rd
generation low phase noise VCO technology and
can achieve 1ps or lower typical rms phase jitter, easily meeting
Ethernet jitter requirements. The 843242 is packaged in a small
16-pin TSSOP package.
Features
•
•
•
•
•
•
•
Two differential LVPECL output pairs
Using a 31.25MHz or 26.041666MHz crystal, the two output
banks can be independently set for 625MHz, 312.5MHz,
156.25MHz or 125MHz
Crystal oscillator interface
RMS Phase Jitter @ 625MHz, (1.875MHz – 20MHz) using a
25MHz crystal: 0.4ps (typical)
Full 3.3V supply mode
0°C to 70°C ambient operating temperature
Lead-free (RoHS 6) packaging
Pin Assignment
nQB
QB
V
CCO_B
SELB1
SELB0
V
CCO_A
QA
nQA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XTAL_IN
XTAL_OUT
V
EE
SELA1
SELA0
V
CC
V
CCA
FB_SEL
843242
16-pin, 4.4mm x 5.0mm TSSOP Package (173 mil)
Block Diagram
SELA[1:0]
0 = Pullup
1 = Pulldown
2
00
01
10
11
00
01
10
11
÷1
÷2
÷4
(default)
÷5
÷1
÷2
÷4
(default)
÷5
QA
nQA
XTAL_IN
OSC
XTAL_OUT
31.25MHz
or
26.041666MHz
Phase
Detector
VCO
625MHz
QB
nQB
Feedback Divider
0 = ÷20
(default)
1 = ÷24
Pulldown
0 = Pulldown
1 = Pullup
FB_SEL
SELB[1:0]
843242 REVISION 1 1/30/15
2
1
©2015 Integrated Device Technology, Inc.
843242 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
nQB
QB
V
CCO_B
SELB1
SELB0
V
CCO_A
QA
nQA
FB_SEL
V
CCA
V
CC
SELA0
SELA1
V
EE
XTAL_OUT
XTAL_IN
Output
Output
Power
Input
Input
Power
Output
Output
Input
Power
Power
Input
Input
Power
Input
Input
Pullup
Pulldown
Pulldown
Pullup
Pulldown
Type
Description
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Output supply pin for QB, nQB outputs.
Division select pin for Bank B.
Default = High.
LVCMOS/LVTTL interface levels.
Division select pins for Bank B.
Default = Low.
LVCMOS/LVTTL interface levels.
Output supply pin for QA, nQA outputs.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Feedback divide select. When LOW (default), the feedback divider is set for
÷20. When HIGH, the feedback divider is set for ÷24. LVCMOS/LVTTL
interface levels.
Analog supply pin.
Core supply pin.
Division select pin for Bank A.
Default = High.
LVCMOS/LVTTL interface levels.
Division select pin for Bank A.
Default = Low.
LVCMOS/LVTTL interface levels.
Negative supply pin.
Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output.
Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
SELA[1:0], SELB[1:0], FB_SEL
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
FEMTOCLOCK
®
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZERS
2
REVISION 1 1/30/15
ICS843242 DATA SHEET
Function Tables
Table 3A. Bank A Frequency Table
Inputs
Crystal Frequency
(MHz)
31.25
31.25
31.25
31.25
26.041666
26.041666
26.041666
26.041666
SELA1
0
0
1
1
0
0
1
1
SELA0
0
1
0
1
0
1
0
1
FB_SEL
0
0
0
0
1
1
1
1
Feedback
Divider
20
20
20
20
24
24
24
24
Bank A
Output Divider
1
2
4
5
1
2
4
5
M/N
Multiplication
Factor
20
10
5
4
24
12
6
4.8
QA, nQA
Output Frequency
(MHz)
625
312.5
156.25
125
625
312.5
156.25
125
Table 3B. Bank B Frequency Table
Inputs
Crystal Frequency
(MHz)
31.25
31.25
31.25
31.25
26.041666
26.041666
26.041666
26.041666
SELB1
0
0
1
1
0
0
1
1
SELB0
0
1
0
1
0
1
0
1
FB_SEL
0
0
0
0
1
1
1
1
Feedback
Divider
20
20
20
20
24
24
24
24
Bank B
Output Divider
1
2
4
5
1
2
4
5
M/N
Multiplication
Factor
20
10
5
4
24
12
6
4.8
QB, nQB
Output Frequency
(MHz)
625
312.5
156.25
125
625
312.5
156.25
125
Table 3C. Output Bank Configuration Select Function Table
Inputs
SELA1
0
0
1
1
SELA0
0
1
0
1
Outputs
QA
÷1
÷2 (default)
÷4
÷5
SELB1
0
0
1
1
Inputs
SELB0
0
1
0
1
Outputs
QB
÷1
÷2
÷4 (default)
÷5
Table 3D. Feedback Divider Configuration Select Function Table
Inputs
FB_DIV
0
1
Feedback Divide
÷20 (default)
÷24
REVISION 1 1/30/15
3
FEMTOCLOCK
®
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZERS
843242 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Junction Temperature, T
J
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
125C
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= V
CCO_A
= V
CCO_B
= 3.3V ±5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
CC
V
CCA
V
CCO_A,
V
CCO_B
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.15
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
CC
3.465
158
15
Units
V
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= V
CCO_A
= V
CCO_B
= 3.3V ±5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
FB_SEL,
SELA1,
SELB0
SELA0,
SELB1
FB_SEL,
SELA1,
SELB0
SELA0,
SELB1
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
Units
V
V
µA
I
IH
Input High
Current
5
µA
I
IL
Input Low
Current
µA
-150
µA
FEMTOCLOCK
®
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZERS
4
REVISION 1 1/30/15
ICS843242 DATA SHEET
Table 4C. LVPECL DC Characteristics,
V
CC
= V
CCO_A
= V
CCO_B
= 3.3V ±5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output
Voltage Swing
Test Conditions
Minimum
V
CCO_X
– 1.4
V
CCO_X
– 2.0
0.6
Typical
Maximum
V
CCO_X
– 0.9
V
CCO_X
– 1.7
1.0
Units
V
V
V
NOTE 1: Output termination with 50 to V
CCO_A, _B
– 2V.
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Load Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
12
26.04166
Test Conditions
Minimum
Typical
Fundamental
31.25
50
7
18
MHz
pF
pF
Maximum
Units
AC Electrical Characteristics
Table 6. AC Characteristics,
V
CC
= V
CCO_A
= V
CCO_B
= 3.3V ±5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
Parameter
Test Conditions
Output Divider = ÷ 1
f
OUT
Output
Frequency
VCO =
625MHz
Output Divider = ÷ 2
Output Divider = ÷ 4
Output Divider = ÷ 5
tsk(o)
Output Skew; NOTE 1, 2
Outputs @ Same Frequency
625MHz, (1.875MHz – 20MHz)
tjit(Ø)
RMS Phase Jitter, (Random);
NOTE 3
312.5MHz, (1.875MHz – 20MHz)
156.25MHz, (1.875MHz – 20MHz)
125MHz, (1.875MHz – 20MHz)
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
SELx[1:0] = 00
SELx[1:0]
00
250
40
45
0.4
0.5
0.5
0.6
650
60
55
Minimum
Typical
625
312.5
156.25
125
45
Maximum
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential
crosspoint.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plots.
REVISION 1 1/30/15
5
FEMTOCLOCK
®
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZERS
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