GS71024T-8 datasheet, PDF - EEWORLD Datasheet

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GS71024T-8: Description64K X 24 STANDARD SRAM, 8 ns, PQFP100; Categorystorage; File Size276KB，13 Pages; ManufacturerETC

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GS71024T-8 Overview

64K X 24 STANDARD SRAM, 8 ns, PQFP100

GS71024T-8 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	100
Maximum operating temperature	70 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	3.6 V
Minimum supply/operating voltage	3.14 V
Rated supply voltage	3.3 V
maximum access time	8 ns
Processing package description	TQFP-100
state	DISCONTINUED
Craftsmanship	CMOS
packaging shape	Rectangle
Package Size	FLATPACK, low PROFILE
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.6500 mm
terminal coating	NOT SPECIFIED
Terminal location	Four
Packaging Materials	Plastic/Epoxy
Temperature level	COMMERCIAL
memory width	24
organize	64K × 24
storage density	1.57E6 deg
operating mode	ASYNCHRONOUS
Number of digits	65536 words
Number of digits	64K
Memory IC type	Standard memory
serial parallel	parallel

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GS71024T/U

TQFP, FP-BGA

Commercial Temp

Industrial Temp

Features

• Fast access time: 8, 9, 10, 12, 15 ns

• CMOS low power operation: 190/170/160/130/110 mA at

minimum cycle time.

• Single 3.3 V ± 0.3 V power supply

• All inputs and outputs are TTL-compatible

• Fully static operation

• Industrial Temperature Option: –40 to 85°C

• Package

T: 100-pin TQFP package

U: 6 mm x 8 mm Fine Pitch Ball Grid Array

GT: Pb-Free 100-pin TQFP available

64K x 24

1.5Mb Asynchronous SRAM

8, 9, 10, 12, 15 ns

3.3 V V

Center V

and V

Fine Pitch BGA Bump Configuration

CE2

CE1

Description

The GS71024 is a high speed CMOS static RAM organized as

65,536 words by 24 bits. Static design eliminates the need for

external clocks or timing strobes. The GS71024 operates on a

single 3.3 V power supply, and all inputs and outputs are TTL-

compatible. The GS71024 is available in a 6 mm x 8 mm Fine

Pitch BGA package, as well as in a 100-pin TQFP package.

6 mm x 8 mm, 0.75 mm Bump Pitch

Top View

Pin Descriptions

Symbol

to A

X/Y

CE1, CE2

Description

Address input

Vector Input

Write enable input

Chip enable input

+3.3 V power supply

Symbol

to DQ

V/S

—

Description

Data input/output

Address Multiplexer Control

Output enable input

—

Ground

Block Diagram

Row

Decoder

Address

Input

A14

A15

X/Y

V/S

CE1

CE2

Memory Array

1024 x 1536

Column

Decoder

Control

I/O Buffer

DQ1

DQ24

Rev: 1.05 11/2004

1/13

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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