EEWORLDEEWORLDEEWORLD

Part Number

Search

GS82032Q-150

Description
64K x 32 2M Synchronous Burst SRAM
File Size518KB,23 Pages
ManufacturerETC
Download Datasheet View All

GS82032Q-150 Overview

64K x 32 2M Synchronous Burst SRAM

Preliminary
GS82032T/Q-150/138/133/117/100/66
TQFP, QFP
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP or QFP package
-150 -138 -133 -117 -100
Pipeline tCycle 6.6 7.25 7.5 8.5
10
3-1-1-1
t
KQ
3.8
4
4
4.5
5
I
DD
270 245 240 210 180
Flow tCycle 10.5 15
15
15
15
Through t
KQ
9
9.7
10
11
12
2-1-1-1
I
DD
170 120 120 120 120
-66
12.5
6
150
20
18
95
Unit
ns
ns
mA
ns
ns
mA
64K x 32
2M Synchronous Burst SRAM
Flow Through/Pipeline Reads
150 MHz–66 MHz
9 ns–18 ns
3.3 V V
DD
3.3 V and 2.5 V I/O
The function of the Data Output register can be controlled by
the user via the FT mode pin/bump (Pin 14 in the TQFP, Bump
1F in the FP-BGA). Holding the FT mode pin/bump low,
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipeline mode, activating the rising-edge-triggered
Data Output Register.
SCD Pipelined Reads
The GS82032 is an SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are
also available. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Functional Description
Applications
The GS82032 is a 2,097,152-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications
ranging from DSP main store to networking chip set support.
Core and Interface Voltages
The GS82032 operates on a 3.3 V power supply and all inputs/
outputs are 3.3 V- and 2.5 V-compatible. Separate output
power (V
DDQ
) pins are used to decouple output noise from the
internal circuit.
Controls
Addresses, data I/Os, chip enables (E
1
, E
2
, E
3
), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Rev: 1.04 2/2001
1/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
How to install goahead webserver under linux?
I just started learning Linux! I don't know how to install goahead in Linux. I have tried to install software using the source code, but it doesn't seem to work! It seems that I can't make install. Ho...
skyzxcvbnm Linux and Android
Data Acquisition System Using DSP+FPGA
DSP TMS320F28335 FPGA EP3C16Q240 FPGA is used for ADDA timing control DSP is used for processing Just upload the pictureQQ956250037...
yicunyu DSP and ARM Processors
TSD circuit
What is a TSD circuit?...
梦溪开物 Analog electronics
Electronic Engineering Drawing Manual Drawing Standards Legend
Electronic Engineering Drawing Manual Drawing Standards Legend...
呱呱 MCU
What is the safe distance between 3kvdc and ground? What is the minimum distance on pcb?
Dear heroes, I encountered a PCB wiring problem. I would like to ask you two questions. What is the safe distance between 3kvdc and the ground? What is the minimum distance on the PCB ? High voltage d...
威海佟 PCB Design
A few questions for help
I haven't posted for a long time, so I'll ask netizens for help with the questions I've collected recently. 1. Is there any software for duplicate image recognition (including emoticon recognition and...
sanhuasr Talking

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 6  2909  2118  838  2128  1  59  43  17  12 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号