Am29SL160C
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
21635
Revision
C
Amendment
+3
Issue Date
November 1, 2004
A D V A N C E
I N F O R M A T I O N
THIS PAGE LEFT INTENTIONALLY BLANK.
2
Am29SL160C
November 1, 2004
Am29SL160C
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 1.8 Volt-only Super Low Voltage Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■
Secured Silicon (SecSi) Sector: 256-byte sector
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function. ExpressFlash option allows entire sector to
be available for factory-secured data
—
Customer lockable:
Customer may program own
custom data. Once locked, data cannot be changed
■
Zero Power Operation
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero
■
Package options
— 48-ball FBGA
— 48-pin TSOP
■
Top or bottom boot block
■
Manufactured on 0.32 µm process technology
■
Compatible with JEDEC standards
— Pinout and software compatible with single-power-
supply flash standard
SOFTWARE FEATURES
■
Supports Common Flash Memory Interface (CFI)
■
Erase Suspend/Erase Resume
— Suspends erase operations to allow programming in
same bank
■
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
■
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
■
Any combination of sectors can be erased
■
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
■
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to reading array data
■
WP#/ACC input pin
— Write protect (WP#) function allows protection of two
outermost boot sectors, regardless of sector protect status
— Acceleration (ACC) function accelerates program
timing
■
Sector protection
— Hardware method of locking a sector, either in-
system or using programming equipment, to prevent
any program or erase operation within that sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
PERFORMANCE CHARACTERISTICS
■
High performance
— Access time as fast 90 ns
— Program time: 8 µs/word typical using Accelerate
■
Ultra low power consumption (typical values)
— 1 mA active read current at 1 MHz
— 5 mA active read current at 5 MHz
— 1 µA in standby or automatic sleep mode
■
Minimum 1 million erase cycles guaranteed per
sector
■
20 Year data retention at 125°C
— Reliable operation for the life of the system
This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may
be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
21635
Rev:
C
Amendment/+3
Issue Date:
November 1, 2004
Refer to AMD’s Website (www.amd.com) for the latest information.
GENERAL DESCRIPTION
The Am29SL160C is a 16 Mbit, 1.8 V volt-only Flash
memory organized as 2,097,152 bytes or 1,048,576
words. The data appears on DQ0–DQ15. The device is
offered in 48-pin TSOP and 48-ball FBGA packages.
The word-wide data (x16) appears on DQ15–DQ0; the
byte-wide (x8) data appears on DQ7–DQ0. This device is
designed to be programmed and erased in-system with a
single 1.8 volt V
CC
supply. No V
PP
is required for program
or erase operations. The device can also be programmed
in standard EPROM programmers.
The standard device offers access times of 90, 100,
120, or 150 ns, allowing microprocessors to operate
without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device requires only a
single 1.8 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The
Unlock Bypass
mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase
command sequence. This initiates the
Embedded
Erase
algorithm—an internal algorithm that automati-
cally preprograms the array (if it is not already
programmed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits.
After a program or erase cycle
completes, the device is ready to read array data or
accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write operations
during power transitions. The
hardware sector pro-
tection
feature disables both program and erase
operations in any combination of the sectors of
memory. This is achieved in-system or via program-
ming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor to
read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses are stable for a specified amount of time, the
device enters the
automatic sleep mode.
The system
can also place the device into the
standby mode.
Power consumption is greatly reduced in both modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
4
Am29SL160C
November 1, 2004
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7
Special Handling Instructions for FBGA Packages .................. 8
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Am29SL160C Device Bus Operations .............................11
Figure 4. Erase Operation.............................................................. 27
Command Definitions ............................................................. 28
Table 12. Am29SL160C Command Definitions ............................. 28
Write Operation Status . . . . . . . . . . . . . . . . . . . . 29
DQ7: Data# Polling ................................................................. 29
Figure 5. Data# Polling Algorithm .................................................. 29
Word/Byte Configuration ........................................................ 11
Requirements for Reading Array Data ................................... 11
Writing Commands/Command Sequences ............................ 12
Accelerated Program Operation ............................................. 12
Program and Erase Operation Status .................................... 12
Standby Mode ........................................................................ 12
Automatic Sleep Mode ........................................................... 12
RESET#: Hardware Reset Pin ............................................... 12
Output Disable Mode .............................................................. 13
Table 2. Am29SL160CT Top Boot Sector Architecture ..................14
Table 3. Am29SL160CB Bottom Boot Sector Architecture .............15
RY/BY#: Ready/Busy# ............................................................ 30
DQ6: Toggle Bit I .................................................................... 30
DQ2: Toggle Bit II ................................................................... 30
Reading Toggle Bits DQ6/DQ2 ............................................... 30
DQ5: Exceeded Timing Limits ................................................ 31
DQ3: Sector Erase Timer ....................................................... 31
Figure 6. Toggle Bit Algorithm........................................................ 31
Table 13. Write Operation Status ................................................... 32
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 33
Figure 7. Maximum Negative Overshoot Waveform ...................... 33
Figure 8. Maximum Positive Overshoot Waveform........................ 33
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 33
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 9. I
CC1
Current vs. Time (Showing Active and Automatic
Sleep Currents) .............................................................................. 35
Figure 10. Typical I
CC1
vs. Frequency ............................................ 35
Autoselect Mode ..................................................................... 16
Table 4. Am29SL160C Autoselect Codes (High Voltage Method) ..16
Sector/Sector Block Protection and Unprotection .................. 17
Table 5. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................17
Table 6. Bottom Boot Sector/Sector Block
Addresses for Protection/Unprotection ...........................................17
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11. Test Setup..................................................................... 36
Table 14. Test Specifications ......................................................... 36
Figure 12. Input Waveforms and Measurement Levels ................. 36
Write Protect (WP#) ................................................................ 18
Temporary Sector Unprotect .................................................. 18
Figure 1. In-System Sector Protect/Unprotect Algorithms .............. 19
Figure 2. Temporary Sector Unprotect Operation........................... 20
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
Read Operations .................................................................... 37
Figure 13. Read Operations Timings ............................................. 37
Hardware Reset (RESET#) .................................................... 38
Figure 14. RESET# Timings .......................................................... 38
Secured Silicon (SecSi) Sector Flash Memory Region .......... 20
Table 7. SecSi Sector Addresses ...................................................20
Word/Byte Configuration (BYTE#) ........................................ 39
Figure 15. BYTE# Timings for Read Operations............................ 39
Figure 16. BYTE# Timings for Write Operations............................ 39
Hardware Data Protection ...................................................... 20
Low V
CC
Write Inhibit .............................................................. 20
Write Pulse “Glitch” Protection ............................................... 20
Logical Inhibit .......................................................................... 20
Power-Up Write Inhibit ............................................................ 20
Common Flash Memory Interface (CFI) . . . . . . . 21
Table 8. CFI Query Identification String ..........................................21
Table 9. System Interface String .....................................................22
Table 10. Device Geometry Definition ............................................22
Table 11. Primary Vendor-Specific Extended Query ......................23
Erase/Program Operations ..................................................... 40
Figure 17. Program Operation Timings..........................................
Figure 18. Chip/Sector Erase Operation Timings ..........................
Figure 19. Data# Polling Timings (During Embedded Algorithms).
Figure 20. Toggle Bit Timings (During Embedded Algorithms)......
Figure 21. DQ2 vs. DQ6.................................................................
Figure 22. Temporary Sector Unprotect Timing Diagram ..............
Figure 23. Accelerated Program Timing Diagram..........................
Figure 24. Sector Protect/Unprotect Timing Diagram ....................
Figure 25. Alternate CE# Controlled Write Operation Timings ......
41
42
43
43
44
44
45
45
47
Command Definitions . . . . . . . . . . . . . . . . . . . . . 23
Reading Array Data ................................................................ 23
Reset Command ..................................................................... 23
Autoselect Command Sequence ............................................ 24
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 24
Word/Byte Program Command Sequence ............................. 24
Unlock Bypass Command Sequence ..................................... 24
Figure 3. Program Operation .......................................................... 25
Chip Erase Command Sequence ........................................... 26
Sector Erase Command Sequence ........................................ 26
Erase Suspend/Erase Resume Commands ........................... 26
Erase And Programming Performance . . . . . . . 48
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 48
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 48
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 49
TS 048—48-Pin Standard TSOP ............................................ 49
FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8 x 9 mm package .................................................................. 50
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 51
November 1, 2004
Am29SL160C
5
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
