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74AUP1G3208GW125

Description
Logic Gates 1.8V SINGLE SCHMITT
Categorysemiconductor    logic   
File Size237KB,22 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
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Logic Gates 1.8V SINGLE SCHMITT

74AUP1G3208GW125 Parametric

Parameter NameAttribute value
Product CategoryLogic Gates
ManufacturerNXP
RoHSDetails
Logic FamilyAUP
Number of Gates1 Gate
Number of Input Lines3 Input
Number of Output Lines1 Output
High Level Output Current- 4 mA
Low Level Output Current4 mA
Propagation Delay Time18.9 ns
Supply Voltage - Max3.6 V
Supply Voltage - Min0.8 V
Minimum Operating Temperature- 40 C
Maximum Operating Temperature+ 125 C
Mounting StyleSMD/SMT
Package / CaseSOT-363
PackagingReel
FunctionOR-AND
Height1 mm
Length2.2 mm
Logic TypeCMOS
Operating Supply Voltage1.8 V, 2.5 V, 3.3 V
Factory Pack Quantity3000
Width1.35 mm
Unit Weight0.000212 oz
74AUP1G3208
Rev. 7 — 7 March 2017
Low-power 3-input OR-AND gate
Product data sheet
1
General description
The 74AUP1G3208 provides the Boolean function: Y = (A + B) × C. The user can choose
the logic functions OR, AND and OR-AND. All inputs can be connected to V
CC
or GND.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the
device when it is powered down.
2
Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C

74AUP1G3208GW125 Related Products

74AUP1G3208GW125 74AUP1G3208GF132
Description Logic Gates 1.8V SINGLE SCHMITT Logic Gates 1.8V 1G LO-PWR
Product Category Logic Gates Logic Gates
Manufacturer NXP NXP
RoHS Details Details
Logic Family AUP AUP
Number of Gates 1 Gate 1 Gate
Number of Input Lines 3 Input 3 Input
Number of Output Lines 1 Output 1 Output
High Level Output Current - 4 mA - 4 mA
Low Level Output Current 4 mA 4 mA
Propagation Delay Time 18.9 ns 18.9 ns
Supply Voltage - Max 3.6 V 3.6 V
Supply Voltage - Min 0.8 V 0.8 V
Minimum Operating Temperature - 40 C - 40 C
Maximum Operating Temperature + 125 C + 125 C
Mounting Style SMD/SMT SMD/SMT
Package / Case SOT-363 XSON
Function OR-AND OR-AND
Height 1 mm 0.46 mm
Length 2.2 mm 1 mm
Logic Type CMOS CMOS
Operating Supply Voltage 1.8 V, 2.5 V, 3.3 V 1.8 V, 2.5 V, 3.3 V
Factory Pack Quantity 3000 5000
Width 1.35 mm 1 mm
Packaging Reel Cut Tape

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