ASM4SSTVF32852-114BR datasheet, PDF

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ASM4SSTVF32852-114BR: DescriptionD Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 24-Bit, True Output, PBGA114, BGA-114; Categorylogic logic; File Size106KB，13 Pages; ManufacturerPulseCore Semiconductor Corporation

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ASM4SSTVF32852-114BR Overview

D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 24-Bit, True Output, PBGA114, BGA-114

ASM4SSTVF32852-114BR Parametric

Parameter Name	Attribute value
Maker	PulseCore Semiconductor Corporation
package instruction	BGA-114
Reach Compliance Code	unknown
series	SSTV
JESD-30 code	R-PBGA-B114
JESD-609 code	e0
length	16 mm
Logic integrated circuit type	D FLIP-FLOP
Number of digits	24
Number of functions	1
Number of terminals	114
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
propagation delay (tpd)	2.7 ns
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	POSITIVE EDGE
width	5.5 mm
minfmax	200 MHz
Base Number Matches	1

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August

2004

rev 2.0

DDR 24-Bit to 48-Bit Registered Buffer

ASM4SSTVF32852

Features



Differential clock signals.

Supports SSTL_2 class II specifications on

inputs and outputs.

Low voltage operation.



= 2.3V to 2.7V.

To ensure that outputs are at a defined logic state

before a stable clock has been supplied, RESETB must

be held at a logic “Low” level during power-up.

In the DDR DIMM application, RESETB is specified to

be asynchronous with respect to CLK/CLKB. Therefore,

no timing relationship can be guaranteed between the

two signals. When entering a low-power standby state,

the register will be cleared and the outputs will be

driven to a logic “Low” level quickly relative to the time

to disable the differential input receivers. This ensures

there are no “glitches” on any output. However, when

coming out of low power standby state, the register will

become active quickly relative to the time taken to

enable the differential input receivers. When the data

inputs are at a logic level “Low” and the clock is stable

during the “Low-to-High” transition of RESETB until the

input receivers are fully enabled, the design ensures

that the outputs will remain at a logic “Low” level.



Available in 114 ball BGA package.

Industrial temperature range also available.

Product Description

The 24-Bit to 48-Bit ASM4SSTVF32852 is a universal

bus driver designed for 2.3V to 2.7V V

operation and

SSTL_2 I/O levels except for the LVCMOS RESETB

input.

Data flow from D to Q is controlled by the differential

clock (CLK/CLKB) and a control signal (RESETB). The

positive edge of CLK is used to trigger the data flow,

and CLKB is used to maintain sufficient noise margins,

whereas the RESETB, an LVCMOS asynchronous

signal is intended for use at the time of power-up only.

The ASM4SSTVF32852 supports a low power standby

mode of operation. A logic

“Low” level at RESETB,

assures that all internal registers and outputs (Q) are

reset to a logic “Low” state, and that all input receivers,

data (D) buffers, and clock (CLK/CLKB) are switched

off. Please note that RESETB must always be

supported with a LVCMOS levels at a valid logic state

since VREF may not be stable during power-up.

Applications



DDR Memory Modules.

Provides complete DDR DIMM logic solution

with ASM5CVF857, ASM4SSTVF16857 and

ASM4SSTVF16859.

SSTL_2 compatible data registers.



Alliance Semiconductor

2575, Augustine Drive



Santa Clara, CA



Tel: 408.855.4900



Fax: 408.855.4999



www.alsc.com

Notice: The information in this document is subject to change without notice.

ASM4SSTVF32852-114BR Related Products

	ASM4SSTVF32852-114BR	ASM4ISSTVF32852-114BT	ASM4SSTVF32852-114BT	ASM4ISSTVF32852-114BR
Description	D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 24-Bit, True Output, PBGA114, BGA-114	D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 24-Bit, True Output, PBGA114, BGA-114	D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 24-Bit, True Output, PBGA114, BGA-114	D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 24-Bit, True Output, PBGA114, BGA-114
Maker	PulseCore Semiconductor Corporation	PulseCore Semiconductor Corporation	PulseCore Semiconductor Corporation	PulseCore Semiconductor Corporation
package instruction	BGA-114	BGA-114	BGA-114	BGA-114
Reach Compliance Code	unknown	unknown	unknown	unknown
series	SSTV	SSTV	SSTV	SSTV
JESD-30 code	R-PBGA-B114	R-PBGA-B114	R-PBGA-B114	R-PBGA-B114
JESD-609 code	e0	e0	e0	e0
length	16 mm	16 mm	16 mm	16 mm
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP
Number of digits	24	24	24	24
Number of functions	1	1	1	1
Number of terminals	114	114	114	114
Maximum operating temperature	70 °C	85 °C	70 °C	85 °C
Output polarity	TRUE	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFBGA	LFBGA	LFBGA	LFBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
propagation delay (tpd)	2.7 ns	2.7 ns	2.7 ns	2.7 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.5 mm	1.5 mm	1.5 mm	1.5 mm
Maximum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V
Minimum supply voltage (Vsup)	2.3 V	2.3 V	2.3 V	2.3 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES
Temperature level	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL
Terminal surface	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD
Terminal form	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	5.5 mm	5.5 mm	5.5 mm	5.5 mm
minfmax	200 MHz	200 MHz	200 MHz	200 MHz
Base Number Matches	1	1	1	1

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