a
FEATURES
Conversion Time: 800 ns
1.25 MHz Throughput Rate
Complete: On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Low Power Dissipation: 570 mW
No Missing Codes Guaranteed
Signal-to-Noise Plus Distortion Ratio
f
IN
= 100 kHz: 70 dB
Pin Configurable Input Voltage Ranges
Twos Complement or Offset Binary Output Data
28-Pin DIP and 28-Pin Surface Mount Package
Out of Range Indicator
AIN1
AIN2
Complete 12-Bit 1.25 MSPS
Monolithic A/D Converter
AD1671
FUNCTIONAL BLOCK DIAGRAM
SHA
OUT
5k
UPO/BPO
ENCODE
V
CC
ACOM
V
EE
V
LOGIC
DCOM
S/H
RANGE
SELECT
5k
X4
3-BIT
FLASH
DAC
3-BIT
FLASH
DAC
COARSE
4-BIT
FLASH
4
8-BIT
LADDER
MATRIX
3
REF IN
REF OUT
2.5V
REF
3
CORRECTION LOGIC
8
FINE
4-BIT
FLASH
4
LATCHES
AD1671
REF COM
OTR
MSB
12
BIT 1 –12
DAV
PRODUCT DESCRIPTION
The AD1671 is a monolithic 12-bit, 1.25 MSPS analog-to-
digital converter with an on-board, high performance sample-
and-hold amplifier (SHA) and voltage reference. The AD1671
guarantees no missing codes over the full operating tempera-
ture range. The combination of a merged high speed bipolar/
CMOS process and a novel architecture results in a combi-
nation of speed and power consumption far superior to pre-
viously available hybrid implementations. Additionally, the
greater reliability of monolithic construction offers improved
system reliability and lower costs than hybrid designs.
The fast settling input SHA is equally suited for both multi-
plexed systems that switch negative to positive full-scale
voltage levels in successive channels and sampling inputs at
frequencies up to and beyond the Nyquist rate. The AD1671
provides both reference output and reference input pins, al-
lowing the on-board reference to serve as a system reference.
An external reference can also be chosen to suit the dc accu-
racy and temperature drift requirements of the application.
The AD1671 uses a subranging flash conversion technique,
with digital error correction for possible errors introduced in
the first part of the conversion cycle. An on-chip timing gen-
erator provides strobe pulses for each of the four internal
flash cycles. A single ENCODE pulse is used to control the
converter. The digital output data is presented in twos
complement or offset binary output format. An out-of-range
signal indicates an overflow condition. It can be used with
the most significant bit to determine low or high overflow.
The performance of the AD1671 is made possible by using high
speed, low noise bipolar circuitry in the linear sections and low
power CMOS for the logic sections. Analog Devices’ ABCMOS-1
process provides both high speed bipolar and 2-micron CMOS
devices on a single chip. Laser trimmed thin-film resistors are
used to provide accuracy and temperature stability.
The AD1671 is available in two performance grades and three
temperature ranges. The AD1671J and K grades are available
over the 0°C to +70°C temperature range. The AD1671A grade
is available over the –40°C to +85°C temperature range. The
AD1671S grade is available over the –55°C to +125°C tempera-
ture range.
PRODUCT HIGHLIGHTS
The AD1671 offers a complete single chip sampling 12-bit,
1.25 MSPS analog-to-digital conversion function in a 28-pin
package.
The AD1671 at 570 mW consumes a fraction of the power of
currently available hybrids.
An OUT OF RANGE output bit indicates when the input sig-
nal is beyond the AD1671’s input range.
Input signal ranges are 0 V to +5 V unipolar or
±
5 V bipolar,
selected by pin strapping, with an input resistance of 10 kΩ.
The input signal range can also be pin strapped for 0 V to +2.5 V
unipolar or
±2.5
V bipolar with an input resistance of 10 MΩ.
Output data is available in unipolar, bipolar offset or bipolar
twos complement binary format.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD1671* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DESIGN RESOURCES
•
AD1671 Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
Symbols and Footprints
DOCUMENTATION
Application Notes
•
AN-348: Avoiding Passive-Component Pitfalls
Data Sheet
•
AD1671 Military Data Sheet
•
AD1671: Complete 12-Bit 1.25 MSPS Monolithic A/D
Converter Data Sheet
DISCUSSIONS
View all AD1671 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
REFERENCE MATERIALS
Technical Articles
•
MS-2210: Designing Power Supplies for High Speed ADC
TECHNICAL SUPPORT
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number.
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AD1671–SPECIFICATIONS
DC SPECIFICATIONS
(T
Parameter
RESOLUTION
CONVERSION TIME
ACCURACY
Integral Nonlinearity (INL)
(S Grade)
Differential Nonlinearity (DNL)
No Missing Codes
Unipolar Offsets
1
(+25°C)
Bipolar Zero
1
(+25°C)
Gain Error
1, 2
(+25°C)
TEMPERATURE COEFFICIENTS
3
Unipolar Offset
(S Grade)
Bipolar Zero
(S Grade)
Gain Error
3
(S Grade)
Gain Error
4
POWER SUPPLY REJECTION
5
V
CC
(+5 V
±
0.25 V)
(S Grade)
V
LOGIC
(+5 V
±
0.25 V)
(S Grade)
V
EE
(–5 V
±
0.25 V)
(S Grade)
ANALOG INPUT
Input Ranges
Bipolar
Unipolar
Input Resistance
(0 V to +2.5 V or
±
2.5 V Range)
(0 V to +5.0 V or
±
5 V Range)
Input Capacitance
Aperture Delay
Aperture Jitter
INTERNAL VOLTAGE REFERENCE
Output Voltage
Output Current
Unipolar Mode
Bipolar Mode
LOGIC INPUTS
High Level Input Voltage, V
IH
Low Level Input Voltage, V
IL
High Level Input Current, I
IH
(V
IN
= V
LOGIC
)
Low Level Input Current, I
LL
(V
IN
= 0 V)
Input Capacitance, C
IN
LOGIC OUTPUTS
High Level Output Voltage, V
OH
(I
OH
= 0.5 mA)
Low Level Output Voltage, V
OL
(I
OL
= 1.6 mA)
POWER SUPPLIES
Operating Voltages
V
CC
V
LOGIC
V
EE
Operating Current
I
CC
I
LOGIC6
I
EE
POWER CONSUMPTION
TEMPERATURE RANGE (SPECIFIED)
J/K
A
S
MIN
to T
MAX
with V
CC
= +5 V
Min
12
5%, V
LOGIC
= +5 V
AD1671J/A/S
Typ
10%, V
EE
= –5 V
Max
800
Min
12
5%, unless otherwise noted)
AD1671K
Typ
Max
800
±
0.7
±
2.5
Units
Bits
ns
LSB
Bits
±
9
±
10
0.35
±
25
±
25
±
30
±
20
±
4
±
4
±
4
LSB
LSB
% FSR
ppm/°C
ppm/°C
ppm/°C
ppm/°C
LSB
LSB
LSB
±
1.5
11
11 Bits Guaranteed
0.1
±
2.5
±
3.0
±
9
±
10
0.35
±
25
±
25
±
25
±
30
±
30
±
40
±
20
±
4
±
5
±
4
±
5
±
4
±
5
12
12 Bits Guaranteed
0.1
–2.5
–5.0
0
0
8
10
10
10
15
20
2.5
+2.5
+5.0
+2.5
+5.0
12
–2.5
–5.0
0
0
8
10
10
10
15
20
2.5
+2.5
+5.0
+2.5
+5.0
12
Volts
Volts
Volts
Volts
MΩ
kΩ
pF
ns
ps
Volts
mA
mA
Volts
Volts
µA
µA
pF
Volts
Volts
2.475
2.525
+2.5
+1.0
2.475
2.525
+2.5
+1.0
2.0
–10
–10
5
2.4
0.4
0.8
+10
+10
2.0
–10
–10
5
2.4
0.4
0.8
+10
+10
+4.75
+4.5
–4.75
55
3
–55
570
0
–40
–55
+5.25
+5.5
–5.25
68
5
–68
750
+70
+85
+125
+4.75
+4.5
–4.75
55
3
–55
570
0
–40
–55
+5.25
+5.5
–5.25
68
5
–68
750
+70
+85
+125
Volts
Volts
Volts
mA
mA
mA
mW
°C
°C
°C
NOTES
1
Adjustable to zero with external potentiometers.
2
Includes internal voltage reference error.
3
+25°C to T
MIN
and +25°C to T
MAX
4
Excludes internal reference drift.
5
Change in gain error as a function of the dc supply voltage.
6
Tested under static conditions. See Figure 15 for typical curve of I
LOGIC
vs. load capacitance at maximum t
C
.
Specifications subject to change without notice.
–2–
REV. B
AD1671
AC SPECIFICATIONS
Parameter
SIGNAL-TO-NOISE PLUS DISTORTION RATIO
(S/N + D)
–0.5 dB Input
–20 dB Input
EFFECTIVE NUMBER OF BITS (ENOB)
TOTAL HARMONIC DISTORTION (THD)
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
SMALL SIGNAL BANDWIDTH
FULL POWER BANDWIDTH
INTERMODULATION DISTORTION (IMD)
2
2nd Order Products
3rd Order Products
(T
MIN
to T
MAX
with V
CC
= +5 V 5%, V
LOGIC
= +5 V
f
lNPUT
= 1OO kHz, unless otherwise noted)
1
Min
10%, V
EE
= –5 V
5%, f
SAMPLE
= 1 MSPS,
AD1671K
Typ
Max
AD1671J/A/S
Typ
Max
Min
Units
68
11.2
70
50
68
11.2
71
51
dB
dB
Bits
–80
–80
12
2
–80
–85
–75
–77
–83
–81
12
2
–75
–77
dB
dB
MHz
MHz
–75
–75
–80
–85
–75
–75
dB
dB
NOTES
1
f
IN
amplitude = –0.5 dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a 0 dB (
±
5 V) input signal, unless otherwise
indicated.
2
f
A
= 99 kHz, f
B
= 100 kHz with f
SAMPLE
= 1 MSPS.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Parameters
(For all grades T
MIN
to T
MAX
with V
CC
= +5 V 5%, V
LO61C
= +5 V 10%,
V
EE
= –5 V 5%; V
IL
= 0.8 V, V
IH
= 2.0 V, V
OL
= 0.4 V and V
OH
= 2.4 V)
Symbol
t
C
F
S
t
ENC
t
ENCL
t
DAV
t
F
t
R
t
DD1
t
SS2
Min
Typ
Max
800
1.25
50
300
Units
ns
MSPS
ns
ns
ns
ns
ns
ns
ns
Conversion Time
Sample Rate
ENCODE Pulse Width High (Figure 1a)
ENCODE Pulse Width Low (Figure 1b)
DAV Pulse Width
ENCODE Falling Edge Delay
Start New Conversion Delay
Data and OTR Delay from DAV Falling Edge
Data and OTR Valid before DAV Rising Edge
20
20
150
0
0
20
20
75
75
NOTES
1
t
DD
is measured from when the falling edge of DAV crosses 0.8 V to when the output crosses 0.4 V or 2.4 V with a 25 pF load capacitor on each output pin.
2
t
SS
is measured from when the outputs cross 0.4 V or 2.4 V to when the rising edge of DAV crosses 2.4 V with a 25 pF load capacitor on each output pin.
Specifications subject to change without notice.
t
ENC
ENCODE
t
C
t
C
t
DAV
t
ENCL
t
R
ENCODE
t
F
t
DAV
DAV
t
R
DAV
t
DD
BIT 1–12
MSB, OTR
DATA 0 (PREVIOUS)
t
SS
DATA 1
t
DD
BIT 1–12
MSB, OTR
DATA 0 (PREVIOUS)
t
SS
DATA 1
Figure 1a. Encode Pulse HIGH
Figure 1b. Encode Pulse LOW
REV. B
–3–
AD1671
PIN DESCRIPTION
Symbol
ACOM
AIN
Pin No.
27
22, 23
Type
P
AI
Name and Function
Analog Ground.
Analog Inputs, AIN1 and AIN2. The AD1671 can be pin strapped for four input ranges:
Range
0 to +2.5 V,
±
2.5 V
0 to +5 V,
±
5 V
Pin Strap
Connect AIN1 to AIN2
Connect AIN1 or AIN2 to ACOM
Signal Input
AIN1 or AIN2
AIN1 or AIN2
BIT 1 (MSB)
BIT 12 (LSB)
BPO/UPO
DAV
13
2
26
16
DO
DO
DO
AI
DO
Most Significant Bit.
Data Bits 2 through 11.
Least Significant Bit.
Bipolar or Unipolar Configuration Pin. See section on Input Range Connections for details.
Data Available Output. The rising edge of DAV indicates an end of conversion and can be used
to latch current data into an external register. The falling edge of DAV can be used to latch
previous dam into an external register.
Digital Ground.
The analog input is sampled on the rising edge of ENCODE.
Inverted Most Significant Bit. Provides twos complement output data format.
Out of Range is Active HIGH when the analog input is out of range. See Output Data Format,
Table III.
REF COM is the internal reference ground pin. REF COM should be connected as indicated
in the Grounding and Decoupling Rules and Optional External Reference Connection Sections.
REF IN is the external 2.5 V reference input.
REF OUT is the internal 2.5 V reference output.
No Connect for bipolar input ranges. Connect SHA OUT to BPO/UPO for unipolar input ranges.
+5 V Analog Power.
–5 V Analog Power.
+5 V Digital Power.
BIT 2–BIT 11 12-3
DCOM
ENCODE
MSB
OTR
REF COM
REF IN
REF OUT
SHA OUT
V
CC
V
EE
V
LOGIC
19
17
14
15
20
24
21
25
28
1
18
P
DI
DO
DO
AI
AI
AO
AO
P
P
P
TYPE: AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Outputs; P = Power.
PIN CONFIGURATION
V
EE
BIT 12 (LSB)
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
28 V
CC
27
26
25
24
23
ACOM
BPO/UPO
SHA OUT
REF IN
AIN1
AIN2
REF OUT
1
2
3
4
5
6
7
8
9
AD1671
TOP VIEW
(Not to Scale)
22
21
20 REF COM
19 DCOM
18 V
LOGIC
17 ENCODE
16
DAV
BIT 4 10
BIT 3 11
BIT 2 12
BIT 1 (MSB) 13
MSB 14
15 OTR
–4–
REV. B
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