IS43DR16640B-25EBL-TR datasheet, PDF

Datasheet> All Categories > storage> IS43DR16640B-25EBL-TR

IS43DR16640B-25EBL-TR: DescriptionDRAM 1G (64Mx16) 400MHz DDR2 1.8v; Categorystorage; File Size902KB，29 Pages; ManufacturerISSI(Integrated Silicon Solution Inc.); Websitehttp://www.issi.com/

Download Datasheet Parametric View All

IS43DR16640B-25EBL-TR Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	IS43DR16640B-25EBL-TR	-	-	View	Buy Now

IS43DR16640B-25EBL-TR Overview

DRAM 1G (64Mx16) 400MHz DDR2 1.8v

IS43DR16640B-25EBL-TR Parametric

Parameter Name	Attribute value
Product Category	DRAM
Manufacturer	ISSI(Integrated Silicon Solution Inc.)
RoHS	Details
Type	SDRAM - DDR2
Data Bus Width	16 bit
Organization	64 M x 16
Package / Case	BGA-84
Memory Size	1 Gbit
Maximum Clock Frequency	400 MHz
Access Time	2.5 ns
Supply Voltage - Max	1.9 V
Supply Voltage - Min	1.7 V
Supply Current - Max	110 mA
Minimum Operating Temperature	0 C
Maximum Operating Temperature	+ 70 C
Packaging	Reel
Moisture Sensitive	Yes
Mounting Style	SMD/SMT
Operating Supply Voltage	1.8 V
Operating Temperature Range	0 C to + 70 C
Factory Pack Quantity	2500

Preview

Download Datasheet

View All

IS43/46DR81280B(L), IS43/46DR16640B(L)

1Gb (x8, x16) DDR2 SDRAM

FEATURES



Clock frequency up to 400MHz

8 internal banks for concurrent operation

4-bit prefetch architecture

Programmable CAS Latency: 3, 4, 5, 6 and 7

Programmable Additive Latency: 0, 1, 2, 3, 4, 5

and 6

Write Latency = Read Latency-1

Programmable Burst Sequence: Sequential or

Interleave

Programmable Burst Length: 4 and 8

Automatic and Controlled Precharge Command

Power Down Mode

Auto Refresh and Self Refresh

Refresh Interval: 7.8

s

(8192 cycles/64 ms)

ODT (On-Die Termination)

Weak Strength Data-Output Driver Option

Bidirectional differential Data Strobe (Single-

ended data-strobe is an optional feature)

On-Chip DLL aligns DQ and DQs transitions with

CK transitions

DQS# can be disabled for single-ended data

strobe

Read Data Strobe supported (x8 only)

Differential clock inputs CK and CK#

VDD and VDDQ = 1.8V ± 0.1V

PASR (Partial Array Self Refresh)



SSTL_18 interface

tRAS lockout supported

Operating temperature:

Commercial (T

= 0°C to 70°C ; T

= 0°C to 85°C)

Industrial (T

= -40°C to 85°C; T

= -40°C to 95°C)

Automotive, A1 (T

= -40°C to 85°C; T

= -40°C to 95°C)

Automotive, A2 (T

= -40°C to 105°C; T

= -40°C to

105°C)

MARCH 2015

OPTIONS



Configuration:



128Mx8 (16M x 8 x 8 banks)



64Mx16 (8M x 16 x 8 banks)



Package:



60-ball TW-BGA for x8



84-ball TW-BGA for x16



Self-Refresh:



Standard



Low Power (L)

ADDRESS TABLE

Parameter

Row Addressing

Column Addressing

Bank Addressing

Precharge Addressing

128Mx8

A0-A13

A0-A9

BA0-BA2

A10

64Mx16

A0-A12

A0-A9

BA0-BA2

A10

Clock Cycle Timing

-3D

Speed Grade

CL-tRCD-tRP

tCK (CL=3)

tCK (CL=4)

tCK (CL=5)

tCK (CL=6)

tCK (CL=7)

Frequency (max)

DDR2-667D

5-5-5

3.75

333

-25E

DDR2-800E

6-6-6

3.75

2.5

400

-25D

DDR2-800D

5-5-5

3.75

2.5

400

Units

tCK

MHz

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Rev. G

3/25/2015

IS43/46DR81280B(L), IS43/46DR16640B(L)

Functional Description

Power-up and Initialization

DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may

result in undefined operation.

Power-up and Initialization Sequence

The following sequence is required for Power-up and Initialization.

1. Either one of the following sequence is required for Power-up:

A. While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT at a LOW state (all other inputs may be

undefined.) The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to

VDD(Min); and during the VDD voltage ramp, |VDD-VDDQ| ≥ 0.3 V. Once the ramping of the supply voltages is

complete (when VDDQ crosses VDDQ(Min)), the supply voltage specifications provided in the table

Recommended DC

Operating Conditions (SSTL_1.8),

prevail.



VDD, VDDL and VDDQ are driven from a single power converter output, AND



VTT is limited to 0.95V max, AND



VREF tracks VDDQ/2, VREF must be within

300mV with respect to VDDQ/2 during supply ramp time.



VDDQ ≥ VREF must be met at all times

B. While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT at a LOW state (all other inputs may be

undefined, voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DRAM latch-

up. During the ramping of the supply voltages, VDD ≥ VDDL ≥ VDDQ must be maintained and is applicable to both AC

and DC levels until the ramping of the supply voltages is complete, which is when VDDQ crosses VDDQ min. Once the

ramping of the supply voltages is complete, the supply voltage specifications provided in the table

Recommended DC

Operating Conditions (SSTL-1.8),

prevail.



Apply VDD/VDDL before or at the same time as VDDQ.



VDD/VDDL voltage ramp time must be no greater 200 ms from when VDD ramps from 300 mV to VDD(Min) .



Apply VDDQ before or at the same time as VTT.



The VDDQ voltage ramp time from when VDD(Min) is achieved on VDD to the VDDQ(Min) is achieved on VDDQ

must be no greater than 500 ms.

2. Start clock and maintain stable condition.

3. For the minimum of 200 µs after stable power (VDD, VDDL, VDDQ, VREF, and VTT values are in the range of the minimum and

maximum values specified in the table

Recommended DC Operating Conditions (SSTL-1.8))

and stable clock (CK, CK#), then apply

NOP or Deselect and assert a logic HIGH to CKE.

4. Wait minimum of 400 ns then issue a precharge all command. During the 400 ns period, a NOP or Deselect command must be

issued to the DRAM.

5. Issue an EMRS command to EMR(2).

6. Issue an EMRS command to EMR(3).

7. Issue EMRS to enable DLL.

8. Issue a Mode Register Set command for DLL reset.

9. Issue a precharge all command.

10. Issue 2 or more auto-refresh commands.

11. Issue a MRS command with LOW to A8 to initialize device operation. (i.e. to program operating parameters without resetting

the DLL.)

12. Wait at least 200 clock cycles after step 8 and then execute OCD Calibration. EMRS Default command (A9=A8=A7=HIGH)

followed by EMRS OCD Calibration Mode Exit command (A9=A8=A7=LOW) must be issued with other operating parameters of

EMR(1).

13. The DDR2 SDRAM is now ready for normal operation.

Note:

1. To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin.

Rev. G

3/25/2015

Recommended Resources

Fish tank thermostat circuit

Integrated LED control board circuit 04

555 proximity switch circuit diagram

555 dual-tone electronic doorbell circuit (1)

Ward call device circuit

Circuit and turn-off waveform when two reverse blocking IGBTs are connected in reverse parallel

Fabless ASIC design companies adopt the "cost plus pricing" model: July 20, 2006 14:16International Electronics BusinesseSilicon, a fabless ASIC design company, recently said that it has created a new business model that enables it to provide its custom IC developmen...; fighting Analog electronics

There are no DAC related registers in the IAR 54x header file: I'm a beginner in 430 and I'm using 5438. Today I looked at the DAC part in the manual and prepared to write some code, but I found that there is no relevant DAC register in msp430x54x.h. I looked for...; 君宝烧香 Microcontroller MCU

[Group Purchase] EE_FPGA V2.0 Learning Board (welded kit, loose parts, empty PCB optional): EE_FPGA V2.0 supporting device group purchase Note: 1.The infrared interface chip TFDU4100 is not available. First of all , I would like to thank Vishay. The first 10 participants will get TFDU4100 fo...; chenzhufly FPGA/CPLD

How to implement interruption of USB virtual serial port: I am using the Atom Brother USB virtual serial routine. The program is tuned and can send and receive normally. But now I am using the query method in the main function to see if any data has been rec...; vincent.liu stm32/stm8

omapl138 uses UPP to receive FPGA sampling data. I am a novice, please give me some advice!: The program is as follows. The BSL library is used. The DMA description register is rewritten each time. Why can only the first packet of data be received? #include #include "types.h" #include "evmoma...; ksxhksxh DSP and ARM Processors

Please explain the cause of pic compilation error: Red fonts are error prompts, which are errors when calling functions. MPASM 5.20 PIC.ASM 10-9-2009 10:55:46 PAGE 2 LOC OBJECT CODE LINE SOURCE TEXT VALUE 0016 0586 00050 BSF RB,4 0017 0506 00051 BSF R...; langniao Microchip MCU

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components