70T631S10BC8 datasheet, PDF - EEWORLD Datasheet

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70T631S10BC8: DescriptionSRAM 256K X 18 STD-PWR 2.5V DUAL PORT RAM; Categorystorage; File Size234KB，28 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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70T631S10BC8 Overview

SRAM 256K X 18 STD-PWR 2.5V DUAL PORT RAM

70T631S10BC8 Parametric

Parameter Name	Attribute value
Product Category	SRAM
Manufacturer	IDT (Integrated Device Technology, Inc.)
RoHS	No
Package / Case	CABGA-256
Packaging	Cut Tape
Packaging	Reel
Height	1.4 mm
Length	17 mm
Moisture Sensitive	Yes
Factory Pack Quantity	1000
Width	17 mm

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Features

◆

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

◆

HIGH-SPEED 2.5V

IDT70T633/1S

512/256K x 18

ASYNCHRONOUS DUAL-PORT

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

Full hardware support of semaphore signaling between

ports on-chip

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Sleep Mode Inputs on both ports

Supports JTAG features compliant to IEEE 1149.1 in

BGA-208 and BGA-256 packages

Single 2.5V (±100mV) power supply for core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 256-ball Ball Grid Array and 208-ball fine pitch

Ball Grid Array

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

◆

Functional Block Diagram

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

– Commercial: 10/12/15ns (max.)

– Industrial: 10/12ns (max.)

RapidWrite Mode simplifies high-speed consecutive write

cycles

Dual chip enables allow for depth expansion without

external logic

IDT70T633/1 easily expands data bus width to 36 bits or

more using the Master/Slave select when cascading more

than one device

M/S = V

for

BUSY

output flag on Master,

M/S = V

for

BUSY

input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

◆

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

512/256K x 18

MEMORY

ARRAY

I/O

- I/O

17L

Din_L

Din_R

I/O

- I/O

17R

18L

(1)

Address

Decoder

ADDR_L

ADDR_R

Address

Decoder

18R

(1)

TDI

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

TDO

JTAG

TCK

TMS

TRST

R/W

BUSY

L(2,3)

SEM

INT

L(3)

(4)

NOTES:

CONTROL

LOGIC

1. Address A

x is a NC for IDT70T631.

BUSY

is an input as a Slave (M/S=V

) and an output when it is a Master (M/S=V

BUSY

and

INT

are non-tri-state totem-pole outputs (push-pull).

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx,

INTx,

M/S and the

sleep mode pins themselves (ZZx) are not affected during sleep mode.

BUSY

R(2,3)

M/S

SEM

INT

R(3)

5670 drw 01

NOVEMBER 2017

DSC-5670/10

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