PCA9541
2-to-1 I
2
C-bus master selector with interrupt logic and reset
Rev. 07 — 2 July 2009
Product data sheet
1. General description
The PCA9541 is a 2-to-1 I
2
C-bus master selector designed for high reliability dual master
I
2
C-bus applications where system operation is required, even when one master fails or
the controller card is removed for maintenance. The two masters (for example, primary
and back-up) are located on separate I
2
C-buses that connect to the same downstream
I
2
C-bus slave devices. I
2
C-bus commands are sent by either I
2
C-bus master and are used
to select one master at a time. Either master at any time can gain control of the slave
devices if the other master is disabled or removed from the system. The failed master is
isolated from the system and will not affect communication between the on-line master
and the slave devices on the downstream I
2
C-bus.
Two versions are offered for different architectures. PCA9541/01 with channel 0 selected
at start-up and PCA9541/03 with no channel selected after start-up.
The interrupt outputs are used to provide an indication of which master has control of the
bus. One interrupt input (INT_IN) collects downstream information and propagates it to
the 2 upstream I
2
C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let
the previous bus master know that it is not in control of the bus anymore and to indicate
the completion of the bus recovery/initialization sequence. Those interrupts can be
disabled and will not generate an interrupt if the masking option is set.
A bus recovery/initialization if enabled sends nine clock pulses, a not acknowledge, and a
STOP condition in order to set the downstream I
2
C-bus devices to an initialized state
before actually switching the channel to the selected master.
An interrupt is sent to the upstream channel when the recovery/initialization procedure is
completed.
An internal bus sensor senses the downstream I
2
C-bus traffic and generates an interrupt
if a channel switch occurs during a non-idle bus condition. This function is enabled when
the PCA9541 recovery/initialization is not used. The interrupt signal informs the master
that an external I
2
C-bus recovery/initialization needs to be performed. It can be disabled
and an interrupt will not be generated.
The pass gates of the switches are constructed such that the V
DD
pin can be used to limit
the maximum high voltage, which will be passed by the PCA9541. This allows the use of
different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V devices can communicate
with 5 V devices without any additional protection.
The PCA9541 does not isolate the capacitive loading on either side of the device, so the
designer must take into account all trace and device capacitances on both sides of the
device, and pull-up resistors must be used on all channels.
External pull-up resistors pull the bus to the desired voltage level for each channel. All I/O
pins are 6.0 V tolerant.
NXP Semiconductors
PCA9541
2-to-1 I
2
C-bus master selector with interrupt logic and reset
An active LOW reset input allows the PCA9541 to be initialized. Pulling the RESET pin
LOW resets the I
2
C-bus state machine and configures the device to its default state as
does the internal Power-On Reset (POR) function.
2. Features
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
2-to-1 bidirectional master selector
I
2
C-bus interface logic; compatible with SMBus standards
PCA9541/01 powers up with Channel 0 selected
PCA9541/03 powers up with no channel selected and either master can take control of
the bus
Active LOW interrupt input
2 active LOW interrupt outputs
Active LOW reset input
4 address pins allowing up to 16 devices on the I
2
C-bus
Channel selection via I
2
C-bus
Bus initialization/recovery function
Bus traffic sensor
Low R
on
switches
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
No glitch on power-up
Supports hot insertion
Software identical for both masters
Low standby current
Operating power supply voltage range of 2.3 V to 5.5 V
6.0 V tolerant inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: SO16, TSSOP16, HVQFN16
3. Applications
I
I
I
I
High reliability systems with dual masters
Gatekeeper multiplexer on long single bus
Bus initialization/recovery for slave devices without hardware reset
Allows masters without arbitration logic to share resources
PCA9541_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 2 July 2009
2 of 41
NXP Semiconductors
PCA9541
2-to-1 I
2
C-bus master selector with interrupt logic and reset
4. Ordering information
Table 1.
Ordering information
T
amb
=
−
40
°
C to +85
°
C
Type number
PCA9541D/01
PCA9541PW/01
PCA9541BS/01
PCA9541D/03
PCA9541PW/03
PCA9541BS/03
Package
Name
SO16
TSSOP16
HVQFN16
SO16
TSSOP16
HVQFN16
Description
plastic small outline package; 16 leads; body width 3.9 mm
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
Version
SOT109-1
SOT403-1
plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; SOT629-1
body 4
×
4
×
0.85 mm
plastic small outline package; 16 leads; body width 3.9 mm
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT109-1
SOT403-1
plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; SOT629-1
body 4
×
4
×
0.85 mm
5. Marking
Table 2.
Marking codes
Topside mark
PCA9541D/01
9541/01
41/1
PCA9541D/03
9541/03
41/3
Type number
PCA9541D/01
PCA9541PW/01
PCA9541BS/01
PCA9541D/03
PCA9541PW/03
PCA9541BS/03
PCA9541_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 2 July 2009
3 of 41
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