82V3385EQG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > semiconductor> Analog mixed-signal IC> 82V3385EQG

82V3385EQG: DescriptionClock Generators u0026 Support Products Synch Ethernet WAN PLL; Categorysemiconductor Analog mixed-signal IC; File Size875KB，145 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

Download Datasheet Parametric Compare View All

82V3385EQG Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	82V3385EQG	-	-	View	Buy Now

82V3385EQG Overview

Clock Generators u0026 Support Products Synch Ethernet WAN PLL

82V3385EQG Parametric

Parameter Name	Attribute value
Product Category	Clock Generators & Support Products
Manufacturer	IDT (Integrated Device Technology, Inc.)
RoHS	Details
Package / Case	TQFP-100
Packaging	Tray
Height	1.4 mm
Length	14 mm
Moisture Sensitive	Yes
Factory Pack Quantity	90
Width	14 mm

Preview

Download Datasheet

View All

SYNCHRONOUS ETHERNET

WAN PLL

IDT82V3385

Version 6

May 14, 2010

6024 Silver Creek Valley Road, San Jose, CA 95138

Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775

Printed in U.S.A.

Table of Contents

FEATURES .............................................................................................................................................................................. 9

HIGHLIGHTS.................................................................................................................................................................................................... 9

MAIN FEATURES ............................................................................................................................................................................................ 9

OTHER FEATURES ......................................................................................................................................................................................... 9

APPLICATIONS....................................................................................................................................................................... 9

DESCRIPTION....................................................................................................................................................................... 10

FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 11

1 PIN ASSIGNMENT ........................................................................................................................................................... 12

2 PIN DESCRIPTION .......................................................................................................................................................... 13

3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 18

RESET ........................................................................................................................................................................................................... 18

MASTER CLOCK .......................................................................................................................................................................................... 18

INPUT CLOCKS & FRAME SYNC SIGNAL ................................................................................................................................................. 18

3.3.1 Input Clocks .................................................................................................................................................................................... 18

3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 18

3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 19

3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 21

3.5.1 Activity Monitoring ......................................................................................................................................................................... 21

3.5.2 Frequency Monitoring ................................................................................................................................................................... 22

3.6 T0 / T4 DPLL INPUT CLOCK SELECTION .................................................................................................................................................. 23

3.6.1 External Fast Selection (T0 only) .................................................................................................................................................. 23

3.6.2 Forced Selection ............................................................................................................................................................................ 24

3.6.3 Automatic Selection ....................................................................................................................................................................... 24

3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 25

3.7.1 T0 / T4 DPLL Locking Detection ................................................................................................................................................... 25

3.7.1.1 Fast Loss .......................................................................................................................................................................... 25

3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 25

3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 25

3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 25

3.7.2 Locking Status ............................................................................................................................................................................... 25

3.7.3 Phase Lock Alarm (T0 only) .......................................................................................................................................................... 26

3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 27

3.8.1 Input Clock Validity ........................................................................................................................................................................ 27

3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 27

3.8.2.1 Revertive Switch ............................................................................................................................................................... 27

3.8.2.2 Non-Revertive Switch (T0 only) ........................................................................................................................................ 28

3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 28

3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 29

3.9.1 T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 29

3.9.2 T4 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 31

3.10 T0 / T4 DPLL OPERATING MODE ............................................................................................................................................................... 32

3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 32

3.10.1.1 Free-Run Mode ................................................................................................................................................................ 32

3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 32

3.10.1.3 Locked Mode .................................................................................................................................................................... 32

3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 32

3.1

3.2

3.3

Table of Contents

May 14, 2010

IDT82V3385

SYNCHRONOUS ETHERNET WAN PLL

3.11

3.12

3.13

3.14

3.15

3.16

3.17

4.1

5.1

5.2

5.3

5.4

5.5

3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 32

3.10.1.5 Holdover Mode ................................................................................................................................................................. 33

3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 33

3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 33

3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 33

3.10.1.5.4 Manual ........................................................................................................................................................... 33

3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 33

3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 33

3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 33

3.10.2.1 Free-Run Mode ................................................................................................................................................................ 33

3.10.2.2 Locked Mode .................................................................................................................................................................... 33

3.10.2.3 Holdover Mode ................................................................................................................................................................. 34

T0 / T4 DPLL OUTPUT ................................................................................................................................................................................. 35

3.11.1 PFD Output Limit ............................................................................................................................................................................ 35

3.11.2 Frequency Offset Limit .................................................................................................................................................................. 35

3.11.3 PBO (T0 only) ................................................................................................................................................................................. 35

3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 35

3.11.5 Four Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 35

3.11.5.1 T0 Path ............................................................................................................................................................................. 35

3.11.5.2 T4 Path ............................................................................................................................................................................. 36

T0 / T4 APLL ................................................................................................................................................................................................. 37

OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 37

3.13.1 Output Clocks ................................................................................................................................................................................. 37

3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 41

MASTER / SLAVE CONFIGURATION ......................................................................................................................................................... 43

INTERRUPT SUMMARY ............................................................................................................................................................................... 44

T0 AND T4 SUMMARY ................................................................................................................................................................................. 44

POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 45

MASTER / SLAVE APPLICATION ............................................................................................................................................................... 46

4 TYPICAL APPLICATION ................................................................................................................................................. 46

5 MICROPROCESSOR INTERFACE .................................................................................................................................. 47

EPROM MODE .............................................................................................................................................................................................. 47

MULTIPLEXED MODE .................................................................................................................................................................................. 48

INTEL MODE ................................................................................................................................................................................................. 51

MOTOROLA MODE ...................................................................................................................................................................................... 53

SERIAL MODE .............................................................................................................................................................................................. 55

6 JTAG ................................................................................................................................................................................ 57

7 PROGRAMMING INFORMATION .................................................................................................................................... 58

7.1

7.2

REGISTER MAP ............................................................................................................................................................................................ 58

REGISTER DESCRIPTION ........................................................................................................................................................................... 63

7.2.1 Global Control Registers ............................................................................................................................................................... 63

7.2.2 Interrupt Registers ......................................................................................................................................................................... 72

7.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 76

7.2.4 Input Clock Quality Monitoring Configuration & Status Registers ........................................................................................... 87

7.2.5 T0 / T4 DPLL Input Clock Selection Registers ............................................................................................................................. 97

7.2.6 T0 / T4 DPLL State Machine Control Registers ......................................................................................................................... 101

7.2.7 T0 / T4 DPLL & APLL Configuration Registers .......................................................................................................................... 103

7.2.8 Output Configuration Registers .................................................................................................................................................. 116

7.2.9 PBO & Phase Offset Control Registers ...................................................................................................................................... 121

7.2.10 Synchronization Configuration Registers ................................................................................................................................. 122

JUNCTION TEMPERATURE ...................................................................................................................................................................... 124

EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 124

8 THERMAL MANAGEMENT ........................................................................................................................................... 124

8.1

8.2

Table of Contents

May 14, 2010

IDT82V3385

SYNCHRONOUS ETHERNET WAN PLL

9 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 126

9.1

9.2

9.3

ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 126

RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 126

I/O SPECIFICATIONS ................................................................................................................................................................................. 127

9.3.1 CMOS Input / Output Port ............................................................................................................................................................ 127

9.3.2 PECL / LVDS Input / Output Port ................................................................................................................................................ 128

9.3.2.1 PECL Input / Output Port ................................................................................................................................................ 128

9.3.2.2 LVDS Input / Output Port ................................................................................................................................................ 130

9.3.2.3 Single-Ended Input for Differential Input ........................................................................................................................ 131

JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 132

OUTPUT WANDER GENERATION ............................................................................................................................................................ 134

INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 135

OUTPUT CLOCK TIMING ........................................................................................................................................................................... 136

8.3

8.4

HEATSINK EVALUATION .......................................................................................................................................................................... 124

TQFP EPAD THERMAL RELEASE PATH ................................................................................................................................................. 125

9.4

9.5

9.6

9.7

PACKAGE DIMENSIONS.................................................................................................................................................... 142

ORDERING INFORMATION................................................................................................................................................ 145

Table of Contents

May 14, 2010

82V3385EQG Related Products

	82V3385EQG	82V3385EQG8
Description	Clock Generators u0026 Support Products Synch Ethernet WAN PLL	Clock Generators u0026 Support Products 82V3385 Sync E WAN PLL
Product Category	Clock Generators & Support Products	Clock Generators & Support Products
Manufacturer	IDT (Integrated Device Technology, Inc.)	IDT (Integrated Device Technology, Inc.)
RoHS	Details	Details
Packaging	Tray	Reel
Moisture Sensitive	Yes	Yes
Factory Pack Quantity	90	750

Recommended Resources

Cordless phone anti-theft circuit

Using LM1035 pre-amplifier

Power amplifier with simple and supreme sound quality 01

Zener Diode Increases Fixed PNP Regulator Output Voltage Rating

Dynamic scanning display circuit with 5-digit decimal counting

Computer motherboard circuit diagram 440GX_25

Solution to inaccurate AD sampling: 1: The reference voltage needs to be accurate enough. It is recommended to use an external high-precision reference voltage.2: If the PGA is adjustable, the smaller the gain coefficient is, the lower ...; Aguilera Analogue and Mixed Signal

Purchase counters to make physical objects: Who can help me make a counter? Requirement: I want to know how many times this red LED light flashes. Sometimes it flashes fast and sometimes it flashes slow. If interested, please contact me: qq5984...; lilijack2010 Buy&Sell

Zigbee Road 1: Zigbee, it’s not easy to say I love you: Unconsciously, or by chance, just like taking the bus or subway every day, I really started the development of Zigbee. What I mean is that my current job is to develop on the cc2530 chip, although I h...; 辛昕 RF/Wirelessly

Common operational issues of Qingyuefeng software----(Schematic diagram library): [b]1. Why is it that when I place a rectangle or rounded rectangle, it is sometimes just a box? [/b] Answer: It may be related to our default settings, which have been adjusted. In fact, you can chang...; tsingyue PCB Design

DS18B20 one-line multi-point test temperature (with 3-point temperature measurement program): I searched for 18B20 information online, and all of them were multi-interface methods, that is, sending CC to skip ROM instructions. Few people have studied 55 matching ROM instructions, and it was di...; wjzpp MCU

I have just established a company and I want to find some MCU developers: Requirements: Familiar with AVR MCU Contact: yaoyaobidy@163.com...; 明月清风 Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components