DP
AK
BUK6217-55C
N-channel TrenchMOS intermediate level FET
Rev. 3 — 9 July 2012
Product data sheet
1. Product profile
1.1 General description
Intermediate level gate drive N-channel enhancement mode Field-Effect Transistor (FET)
in a plastic package using advanced TrenchMOS technology. This product has been
designed and qualified to the appropriate AEC Q101 standard for use in high performance
automotive applications.
1.2 Features and benefits
AEC Q101 compliant
Suitable for standard and logic level
gate drive sources
Suitable for thermally demanding
environments due to 175 °C rating
1.3 Applications
12 V and 24 V Automotive systems
Electric and electro-hydraulic power
steering
Motors, lamps and solenoid control
Start-Stop micro-hybrid applications
Transmission control
Ultra high performance power
switching
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
drain-source on-state resistance
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
V
GS
= 10 V; T
mb
= 25 °C;
see
Figure 1
T
mb
= 25 °C; see
Figure 2
V
GS
= 10 V; I
D
= 12 A; T
j
= 25 °C;
see
Figure 11
I
D
= 25 A; V
DS
= 44 V; V
GS
= 10 V;
see
Figure 13;
see
Figure 14
I
D
= 44 A; V
sup
≤
55 V; R
GS
= 50
Ω;
V
GS
= 10 V; T
j(init)
= 25 °C;
unclamped
Min
-
-
-
-
Typ
-
-
-
16
Max
55
44
80
19
Unit
V
A
W
mΩ
Static characteristics
Dynamic characteristics
Q
GD
gate-drain charge
-
11.2
-
nC
Avalanche ruggedness
E
DS(AL)S
non-repetitive drain-source
avalanche energy
-
-
45
mJ
NXP Semiconductors
BUK6217-55C
N-channel TrenchMOS intermediate level FET
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G
D
S
D
gate
drain
source
mounting base; connected to drain
mbb076
Simplified outline
mb
Graphic symbol
D
G
S
2
1
3
DPAK (SOT428)
3. Ordering information
Table 3.
Ordering information
Package
Name
BUK6217-55C
DPAK
Description
plastic single-ended surface-mounted package (DPAK); 3 leads
(one lead cropped)
Version
SOT428
Type number
4. Marking
Table 4.
Marking codes
Marking code
BUK6217-55C
Type number
BUK6217-55C
BUK6217-55C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 9 July 2012
2 of 14
NXP Semiconductors
BUK6217-55C
N-channel TrenchMOS intermediate level FET
5. Limiting values
Table 5.
Symbol
V
DS
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
E
DS(AL)R
Limiting values
Parameter
drain-source voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive drain-source
avalanche energy
repetitive drain-source avalanche
energy
T
mb
= 25 °C
pulsed; t
p
≤
10 µs; T
mb
= 25 °C
I
D
= 44 A; V
sup
≤
55 V; R
GS
= 50
Ω;
V
GS
= 10 V; T
j(init)
= 25 °C; unclamped
[3][4][5]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
DC
Pulsed
T
mb
= 25 °C; V
GS
= 10 V; see
Figure 1
T
mb
= 100 °C; V
GS
= 10 V; see
Figure 1
T
mb
= 25 °C; pulsed; t
p
≤
10 µs;
see
Figure 3
T
mb
= 25 °C; see
Figure 2
[1]
[2]
Min
-
-16
-20
-
-
-
-
-55
-55
-
-
-
-
Max
55
16
20
44
31
175
80
175
175
44
175
45
-
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
J
Source-drain diode
Avalanche ruggedness
[1]
[2]
[3]
[4]
[5]
-16V accumulated duration not to exceed 168 hrs
Accumulated pulse duration not to exceed 5mins.
Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
Repetitive avalanche rating limited by an average junction temperature of 170 °C.
Refer to application note AN10273 for further information.
BUK6217-55C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 9 July 2012
3 of 14
NXP Semiconductors
BUK6217-55C
N-channel TrenchMOS intermediate level FET
50
I
D
(A)
40
003aae797
120
P
der
(%)
80
03na19
30
20
40
10
0
0
50
100
150
200
T
mb
(°C)
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Continuous drain current as a function of
mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
003aae798
10
3
I
D
(A)
10
2
Limit R
DSon
= V
DS
/ I
D
t
p
=10
μ
s
100
μ
s
10
DC
1
1 ms
10 ms
100 ms
10
-1
10
-1
1
10
10
2
V
DS
(V)
10
3
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
BUK6217-55C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 9 July 2012
4 of 14
NXP Semiconductors
BUK6217-55C
N-channel TrenchMOS intermediate level FET
6. Thermal characteristics
Table 6.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance from junction to mounting base
Conditions
see
Figure 4
Min
-
Typ
-
Max
1.87
Unit
K/W
10
Z
th(j-mb)
(K/W)
δ
= 0.5
0.2
0.1
0.05
003aae795
1
10
-1
0.02
single shot
P
δ
=
t
p
T
t
p
t
T
10
-2
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
tp (s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK6217-55C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 9 July 2012
5 of 14
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