74LV00DB datasheet, PDF - EEWORLD Datasheet

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74LV00DB: DescriptionLogic Gates QUAD 2-INPUT NAND GATE 3 VOLT; Categorylogic logic; File Size844KB，14 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74LV00DB Overview

Logic Gates QUAD 2-INPUT NAND GATE 3 VOLT

74LV00DB Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	SSOP
package instruction	5.30 MM, PLASTIC, MO-150, SOT337-1, SSOP-14
Contacts	14
Reach Compliance Code	unknown
series	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G14
JESD-609 code	e4
length	6.2 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	NAND GATE
MaximumI(ol)	0.006 A
Humidity sensitivity level	1
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Encapsulate equivalent code	SSOP14,.3
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
method of packing	TUBE
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Sup	18 ns
propagation delay (tpd)	31 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	2 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	1 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	5.3 mm
Base Number Matches	1

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74LV00

Quad 2-input NAND gate

Rev. 4 — 9 December 2015

Product data sheet

1. General description

The 74LV00 is a low-voltage Si-gate CMOS device that is pin and function compatible with

74HC00 and 74HCT00.

The 74LV00 provides a quad 2-input NAND function.

2. Features and benefits



Wide operating voltage: 1.0 V to 5.5 V

Optimized for low voltage applications: 1.0 V to 3.6 V

Accepts TTL input levels between V

= 2.7 V and V

= 3.6 V

Typical output ground bounce < 0.8 V at V

= 3.3 V and T

amb

= 25

C

Typical HIGH-level output voltage (V

) undershoot: > 2 V at V

= 3.3 V and

amb

= 25

C



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V



Multiple package options



Specified from

40 C

to +85

C

and from

40 C

to +125

C

3. Ordering information

Table 1.

Ordering information

Package

Temperature range

74LV00D

74LV00DB

74LV00PW

74LV00BQ

40 C

to +125

C

40 C

to +125

C

40 C

to +125

C

40 C

to +125

C

Name

SO14

SSOP14

TSSOP14

Description

plastic small outline package; 14 leads;

body width 3.9 mm

plastic shrink small outline package; 14 leads;

body width 5.3 mm

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

Version

SOT108-1

SOT337-1

SOT402-1

SOT762-1

Type number

DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad flat package; no leads; 14 terminals;

body 2.5



0.85 mm

74LV00DB Related Products

	74LV00DB	74LV00D	74LV00PW	74LV00PW-T	74LV00N	74LV00D-T	74LV00DB-T
Description	Logic Gates QUAD 2-INPUT NAND GATE 3 VOLT	Logic Gates QUAD 2-INPUT NAND GATE 3 VOLT	Logic Gates QUAD 2-INPUT NAND GATE 3 VOLT	Logic Gates QUAD 2-INPUT NAND GATE 3 VOLT	Logic Gates QUAD 2-INPUT NAND GATE 3 VOLT	Logic Gates QUAD 2-INPUT NAND GATE 3 VOLT	Logic Gates QUAD 2-INPUT NAND GATE 3 VOLT
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	NXP	NXP	NXP	NXP	NXP	NXP	NXP
Parts packaging code	SSOP	SOIC	TSSOP	TSSOP	MO-001	SOIC	SSOP
package instruction	5.30 MM, PLASTIC, MO-150, SOT337-1, SSOP-14	3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-14	4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14	4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14	DIP, DIP14,.3	3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-14	5.30 MM, PLASTIC, MO-150, SOT337-1, SSOP-14
Contacts	14	14	14	14	14	14	14
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown
series	LV/LV-A/LVX/H	LV/LV-A/LVX/H	LV/LV-A/LVX/H	LV/LV-A/LVX/H	LV/LV-A/LVX/H	LV/LV-A/LVX/H	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDIP-T14	R-PDSO-G14	R-PDSO-G14
JESD-609 code	e4	e4	e4	e4	e4	e4	e4
length	6.2 mm	8.65 mm	5 mm	5 mm	19.025 mm	8.65 mm	6.2 mm
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	NAND GATE	NAND GATE	NAND GATE	NAND GATE	NAND GATE	NAND GATE	NAND GATE
MaximumI(ol)	0.006 A	0.006 A	0.006 A	0.006 A	0.006 A	0.006 A	0.006 A
Number of functions	4	4	4	4	4	4	4
Number of entries	2	2	2	2	2	2	2
Number of terminals	14	14	14	14	14	14	14
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SSOP	SOP	TSSOP	TSSOP	DIP	SOP	SSOP
Encapsulate equivalent code	SSOP14,.3	SOP14,.25	TSSOP14,.25	TSSOP14,.25	DIP14,.3	SOP14,.25	SSOP14,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	IN-LINE	SMALL OUTLINE	SMALL OUTLINE, SHRINK PITCH
method of packing	TUBE	TUBE	TUBE	TAPE AND REEL	TUBE	TAPE AND REEL	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260	260	260	260	NOT SPECIFIED	260	260
power supply	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Prop。Delay @ Nom-Sup	18 ns	18 ns	18 ns	18 ns	18 ns	18 ns	18 ns
propagation delay (tpd)	31 ns	31 ns	31 ns	31 ns	31 ns	31 ns	31 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Schmitt trigger	NO	NO	NO	NO	NO	NO	NO
Maximum seat height	2 mm	1.75 mm	1.1 mm	1.1 mm	4.2 mm	1.75 mm	2 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	1 V	1 V	1 V	1 V	1 V	1 V	1 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	NO	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	THROUGH-HOLE	GULL WING	GULL WING
Terminal pitch	0.65 mm	1.27 mm	0.65 mm	0.65 mm	2.54 mm	1.27 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	30	30	NOT SPECIFIED	30	30
width	5.3 mm	3.9 mm	4.4 mm	4.4 mm	7.62 mm	3.9 mm	5.3 mm
Base Number Matches	1	1	1	1	1	1	1
Is it lead-free?	Lead free	Lead free	Lead free	-	Lead free	-	-
Humidity sensitivity level	1	1	1	1	-	1	1
Source Url Status Check Date	-	-	-	2013-06-14 00:00:00	2013-06-14 00:00:00	2013-06-14 00:00:00	2013-06-14 00:00:00

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