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74AC20M

Description
Logic Gates Dual 4-Input NAND
Categorylogic    logic   
File Size195KB,8 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Environmental Compliance
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74AC20M Overview

Logic Gates Dual 4-Input NAND

74AC20M Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSTMicroelectronics
Parts packaging codeSOIC
package instructionSOP, SOP14,.25
Contacts14
Reach Compliance Codecompliant
seriesAC
JESD-30 codeR-PDSO-G14
JESD-609 codee4
length8.65 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.012 A
Number of functions2
Number of entries4
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
method of packingTUBE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3/5 V
Prop。Delay @ Nom-Sup9 ns
propagation delay (tpd)11 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.9 mm
Base Number Matches1
74AC20
DUAL 4-INPUT NAND GATE
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 4ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 2µA(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 20
IMPROVED LATCH-UP IMMUNITY
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74AC20B
74AC20M
DESCRIPTION
The 74AC20 is an advanced high-speed CMOS
DUAL 4-INPUT NAND GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS tecnology.
PIN CONNECTION AND IEC LOGIC SYMBOLS
O
so
b
te
le
ro
P
uc
d
s)
t(
so
b
-O
The internal circuit is composed of 3 stages
including buffer output, which enables high noise
immunity and stable output.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
P
te
le
od
r
s)
t(
uc
T&R
74AC20MTR
74AC20TTR
April 2001
1/8
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