Summary
Atmel's SAM4L series is a member of a family of Flash microcontrollers based
on the high performance 32-bit ARM Cortex-M4 RISC processor running at fre-
quencies up to 48MHz.
The SAM4L series embeds state-of-the-art picoPower technology for ultra-low
power consumption. Combined power control techniques are used to bring
active current consumption down to 90μA/MHz. The device allows a wide range
of options between functionality and power consumption, giving the user the
ability to reach the lowest possible power consumption with the feature set
required for the application. The WAIT and RETENTION modes provide full logic
and RAM retention, associated with fast wake-up capability (<1.5μs) and a very
low consumption of, respectively, 3
μA
and 1.5
μA.
In addition, WAIT mode sup-
ports SleepWalking features. In BACKUP mode, CPU, peripherals and RAM are
powered off and, while consuming less than 0.9μA with external interrupt wake-
up supported.
The SAM4L series offers a wide range of peripherals such as segment LCD con-
troller, embedded hardware capacitive touch (QTouch), USB device &
embedded host, 128-bit AES and audio interfaces in addition to high speed
serial peripherals such as USART, SPI and I
2
C. Additionally the Peripheral Event
System and SleepWalking allows the peripherals to communicate directly with
each other and make intelligent decisions and decide to wake-up the system on
a qualified events on a peripheral level; such as I
2
C address match or and ADC
threshold.
ATSAM---e
ARM-based
Flash MCU
SAM4L Series
Features
•
Core
– ARM
®
Cortex
TM
-M4 running at up to 48MHz
– Memory Protection Unit (MPU)
– Thumb
®
-2 instruction set
•
picoPower
®
Technology for Ultra-low Power Consumption
– Active mode downto 90µA/MHz with configurable voltage scaling
– High performance and efficiency: 28 coremark/mA
– Wait mode downto 3µA with fast wake-up time (<1.5µs) supporting SleepWalking
– Full RAM and Logic Retention mode downto 1.5µA with fast wake-up time (<1.5µs)
– Ultra low power Backup mode with/without RTC downto 1,5/0.9µA
•
Memories
– From 128 to 512Kbytes embedded Flash, 64-bit wide access,
• 0 wait-state capability up to 24MHz
– up to 64Kbytes embedded SRAM
•
System Functions
– Embedded voltage linear and switching regulator for single supply operation
– Two Power-on-Reset and Two Brown-out Detectors (BOD)
– Quartz or ceramic resonator oscillators: 0.6 to 30MHz main power with Failure
Detection and low power 32.768 kHz for RTC or device clock
– High precision 4/8/12MHz factory trimmed internal RC oscillator
– Slow Clock Internal RC oscillator as permanent low-power mode device clock
– High speed 80MHz internal RC oscillator
– Low power 32kHz internal RC oscillator
Summary
42023HS–11/2016
ATSAM4L8/L4/L2
– PLL up to 240MHz for device clock and for USB
– Digital Frequency Locked Loop (DFLL) with wide input range
– Up to 16 peripheral DMA (PDCA) channels
Peripherals
– USB 2.0 Device and Embedded Host: 12 Mbps, up to 8 bidirectional Endpoints and Multi-packet Ping-pong Mode. On-
Chip Transceiver
– Liquid Crystal Display (LCD) Module with Capacity up to 40 Segments and up to 4 Common Terminals
– One USART with ISO7816, IrDA®, RS-485, SPI, Manchester and LIN Mode
– Three USART with SPI Mode
– One PicoUART for extended UART wake-up capabilities in all sleep modes
– Windowed Watchdog Timer (WDT)
– Asynchronous Timer (AST) with Real-time Clock Capability, Counter or Calendar Mode Supported
– Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency
– Six 16-bit Timer/Counter (TC) Channels with capture, waveform, compare and PWM mode
– One Master/Slave Serial Peripheral Interface (SPI) with Chip Select Signals
– Four Master and Two Slave Two-wire Interfaces (TWI), up to 3.4Mbit/s I
2
C-compatible
– One Advanced Encryption System (AES) with 128-bit key length
– One 16-channel ADC 300Ksps (ADC) with up to 12 Bits Resolution
– One DAC 500Ksps (DACC) with up to 10 Bits Resolution
– Four Analog Comparators (ACIFC) with Optional Window Detection
– Capacitive Touch Module (CATB) supporting up to 32 buttons
– Audio Bitstream DAC (ABDACB) Suitable for Stereo Audio
– Inter-IC Sound (IISC) Controller, Compliant with Inter-IC Sound (I
2
S) Specification
– Peripheral Event System for Direct Peripheral to Peripheral Communication
– 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
– Random generator (TRNG)
– Parallel Capture Module (PARC)
– Glue Logic Controller (GLOC)
I/O
– Up to 75 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and slew-rate
control
– Up to Six High-drive I/O Pins
Single 1.68-3.6V Power Supply
Packages
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/100-ball VFBGA, 7x7 mm, pitch 0.65 mm
– 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/64-pad QFN 9x9 mm, pitch 0.5 mm
– 64-ball WLCSP, 4,314x4,434 mm, pitch 0.5 mm for SAM4LC4/2 and SAM4LS4/2 series
– 64-ball WLCSP, 5,270x5,194 mm, pitch 0.5 mm for SAM4LC8 and SAM4LS8 series
– 48-lead LQFP, 7 x 7 mm, pitch 0.5 mm/48-pad QFN 7x7 mm, pitch 0.5 mm
•
•
•
•
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42023HS–SAM–11/2016
ATSAM4L8/L4/L2
1. Description
Atmel's SAM4L series is a member of a family of Flash microcontrollers based on the high per-
formance 32-bit ARM Cortex-M4 RISC processor running at frequencies up to 48MHz.
The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con-
troller for supporting modern and real-time operating systems.
The ATSAM4L8/L4/L2 embeds state-of-the-art picoPower technology for ultra-low power con-
sumption. Combined power control techniques are used to bring active current consumption
down to 90µA/MHz. The device allows a wide range of options between functionality and power
consumption, giving the user the ability to reach the lowest possible power consumption with the
feature set required for the application. On-chip regulator improves power efficiency when used
in swichting mode with an external inductor or can be used in linear mode if application is noise
sensitive.
The ATSAM4L8/L4/L2 supports 4 power saving strategies. The SLEEP mode put the CPU in
idle mode and offers different sub-modes which automatically switch off/on bus clocks, PLL,
oscillators. The WAIT and RETENTION modes provide full logic and RAM retention, associated
with fast wake-up capability (<1.5µs) and a very low consumption of, respectively, 3 µA and 1.5
µA. In addition, WAIT mode supports SleepWalking features. In BACKUP mode, CPU, peripher-
als and RAM are powered off and, while consuming less than 0.5µA, the device is able to wake-
up from external interrupts.
The ATSAM4L8/L4/L2 incorporates on-chip Flash tightly coupled to a low power cache
(LPCACHE) for active consumption optimization and SRAM memories for fast access.
The LCD controller is intended for monochrome passive liquid crystal display (LCD) with up to 4
Common terminals and up to 40 Segments terminals. Dedicated Low Power Waveform, Con-
trast Control, Extended Interrupt Mode, Selectable Frame Frequency and Blink functionality are
supported to offload the CPU, reduce interrupts and reduce power consumption. The controller
includes integrated LCD buffers and integrated power supply voltage.
The low-power and high performance capacitive touch module (CATB) is introduced to meet the
demand for a low power capacitive touch solution that could be used to handle buttons, sliders
and wheels. The CATB provides excellent signal performance, as well as autonomous touch
and proximity detection for up to 32 sensors. This solution includes an advanced sequencer in
addition to an hardware filtering unit.
The Advanced Encryption Standard module (AESA) is compliant with the
FIPS (Federal Infor-
mation Processing Standard) Publication 197, Advanced Encryption Standard (AES),
which
specifies a symmetric block cipher that is used to encrypt and decrypt electronic data.
Encryp-
tion
is the transformation of a usable message, called the
plaintext,
into an unreadable form,
called the
ciphertext.
On the other hand,
decryption
is the transformation that recovers the plain-
text from the ciphertext. AESA supports 128 bits cryptographic key sizes.
The Peripheral Direct Memory Access (DMA) controller enables data transfers between periph-
erals and memories without processor involvement. The Peripheral DMA controller drastically
reduces processing overhead when transferring continuous and large data streams.
The Peripheral Event System (PES) allows peripherals to receive, react to, and send peripheral
events without CPU intervention. Asynchronous interrupts allow advanced peripheral operation
in low power modes.
The Power Manager (PM) improves design flexibility and security. The Power Manager supports
SleepWalking functionality, by which a module can be selectively activated based on peripheral
3
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
events, even in sleep modes where the module clock is stopped. Power monitoring is supported
by on-chip Power-on Reset (POR18, POR33), Brown-out Detectors (BOD18, BOD33). The
device features several oscillators, such as Phase Locked Loop (PLL), Digital Frequency
Locked Loop (DFLL), Oscillator 0 (OSC0), Internal RC 4,8,12MHz oscillator (RCFAST), system
RC oscillator (RCSYS), Internal RC 80MHz, Internal 32kHz RC and 32kHz Crystal Oscillator.
Either of these oscillators can be used as source for the system clock. The DFLL is a program-
mable internal oscillator from 40 to 150MHz. It can be tuned to a high accuracy if an accurate
reference clock is running, e.g. the 32kHz crystal oscillator.
The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the soft-
ware. This allows the device to recover from a condition that has caused the system to be
unstable.
The Asynchronous Timer (AST) combined with the 32kHz crystal oscillator supports powerful
real-time clock capabilities, with a maximum timeout of up to 136 years. The AST can operate in
counter or calendar mode.
The Frequency Meter (FREQM) allows accurate measuring of a clock frequency by comparing it
to a known reference clock.
The Full-speed USB 2.0 device and embedded host interface (USBC) supports several USB
classes at the same time utilizing the rich end-point configuration.
The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be inde-
pendently programmed to perform frequency measurement, event counting, interval
measurement, pulse generation, delay timing, and pulse width modulation.
The ATSAM4L8/L4/L2 also features many communication interfaces, like USART, SPI, or TWI,
for communication intensive applications. The USART supports different communication modes,
like SPI Mode and LIN Mode.
A general purpose 16-channel ADC is provided, as well as four analog comparators (ACIFC).
The ADC can operate in 12-bit mode at full speed. The analog comparators can be paired to
detect when the sensing voltage is within or outside the defined reference window.
Atmel offers the QTouch Library for embedding capacitive touch buttons, sliders, and wheels
functionality. The patented charge-transfer signal acquisition offers robust sensing and includes
fully debounced reporting of touch keys as well as Adjacent Key Suppression
®
(AKS
®
) technol-
ogy for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows
you to explore, develop, and debug your own touch applications.
The Audio Bitstream DAC (ABDACB) converts a 16-bit sample value to a digital bitstream with
an average value proportional to the sample value. Two channels are supported, making the
ABDAC particularly suitable for stereo audio.
The Inter-IC Sound Controller (IISC) provides a 5-bit wide, bidirectional, synchronous, digital
audio link with external audio devices. The controller is compliant with the Inter-IC Sound (I2S)
bus specification.
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42023HS–SAM–11/2016
ATSAM4L8/L4/L2
2. Overview
2.1
Block Diagram
Figure 2-1.
Block Diagram
System
TAP
TCK
TDO
TDI
TMS
JTAG &
Serial Wire
System
Management
Access Port
In-Circuit
Emulator
ARM Cortex-M4 Processor
Fmax 48 MHz
MEMORY PROTECTION UNIT
Instruction/
Data
M
M
M
System
S
HRAM
CONTROLLER
64/32 KB
RAM
128-bit
AES
DP
DMA
S
S
S
HIGH SPEED
BUS MATRIX
NVIC
S
FLASH
512/256/128 KB
CONTROLLER
FLASH
LOW POWER CACHE
USBC
DM
8 EndPoints
S
CONFIGURATION
S
REGISTERS BUS
S
M
VDDIN
VDDOUT
VDDCORE
LDO/
SWITCHING
REGULATOR
HSB-PB
BRIDGE B
HSB-PB
BRIDGE D
HSB-PB
BRIDGE C
HSB-PB
BRIDGE A
PERIPHERAL
DMA
CONTROLLER
RC32K
GENERALPURPOSE I/Os
XIN32
XOUT32
BACKUP
SYSTEM
CONTROL
INTERFACE
USART0
USART1
USART2
USART3
SPI
TWI MASTER 0
TWI MASTER 1
TWI MASTER 2
TWI MASTER 3
TWI SLAVE 0
TWI SLAVE 1
LCD
CONTROLLER
RXD
TXD
CLK
RTS, CTS
SCK
MISO, MOSI
NPCS[3..0]
TWCK
TWD
BACKUP
POWER MANAGER
BACKUP
REGISTERS
EXTINT[8..1]
NMI
DMA
ASYNCHRONOUS
TIMER
WATCHDOG
TIMER
RXD
PERIPHERAL EVENT CONTROLLER
SEG[39..0]
COM[3..0]
BIASL,BIASH
CAPH,CAPL
ISCK
IWS
ISDI
ISDO
IMCK
CLK
GENERAL PURPOSE I/Os
EXTERNAL INTERRUPT
CONTROLLER
DMA
PA
PB
PC
DMA
OSC32
DMA
TWCK
TWD
DMA
INTER-IC SOUND
CONTROLLER
PICOUART
DMA
BACKUP DOMAIN
POWER MANAGER
RESETN
DMA
PA
PB
PC
AUDIO BITSTREAM
DAC
16-CHANNEL
12-bit ADC
INTERFACE
10-bit DAC
INTERFACE
CAPACITIVE TOUCH
MODULE
PARALLEL CAPTURE
CONTROLLER
GLUE LOGIC
CONTROLLER
TIMER/COUNTER 0
TIMER/COUNTER 1
ABDAC[1..0]
ABDACN[1..0]
DMA
CLOCK
CONTROLLER
RESET
CONTROLLER
GCLK_IN[1:0]
GCLK[3:0]
TRIGGER
AD[14..0]
ADVREFP
DMA
SLEEP
CONTROLLER
DACOUT
RCSYS
RCFAST
DMA
SENSE[69..0]
DIS
PCCK
PCEN1,PCEN2
PCDATA[7..0]
IN[7..0]
OUT[1..0]
CLK[2..0]
RC80M
XIN0
XOUT0
SYSTEM CONTROL
INTERFACE
GENERIC
CLOCK
OSC0
DFLL
PLL
FREQUENCY METER
DMA
B[2..0]
A[2..0]
ACAP[3..0]
ACAN[3..0]
ACREFN
AC INTERFACE
PAD_EVT[3..0]
TRUE RANDOM
GENERATOR
32-BIT CRC
CALCULATION UNIT
5
42023HS–SAM–11/2016
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