PIC32
PIC32 Flash Programming Specification
1.0
DEVICE OVERVIEW
2.0
PROGRAMMING OVERVIEW
This document defines the Flash programming
specification for the PIC32 family of 32-bit
microcontrollers.
This programming specification is designed to guide
developers of external programmer tools. Customers
who are developing applications for PIC32 devices
should use development tools that already provide
support for device programming.
The major topics of discussion include:
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Section 1.0 “Device Overview”
Section 2.0 “Programming Overview”
Section 3.0 “Programming Steps”
Section 4.0 “Connecting to the Device”
Section 5.0 “EJTAG vs. ICSP”
Section 6.0 “Pseudo Operations”
Section 7.0 “Entering 2-Wire Enhanced ICSP
Mode”
Section 8.0 “Check Device Status”
Section 9.0 “Erasing the Device”
Section 10.0 “Entering Serial Execution Mode”
Section 11.0 “Downloading the Programming
Executive (PE)”
Section 12.0 “Downloading a Data Block”
Section 13.0 “Initiating a Page Erase”
Section 14.0 “Initiating a Flash Row Write”
Section 15.0 “Verify Device Memory”
Section 16.0 “Exiting Programming Mode”
Section 17.0 “The Programming Executive”
Section 18.0 “Checksum”
Section 19.0 “Configuration Memory and Device
ID”
Section 20.0 “TAP Controllers”
Section 21.0 “AC/DC Characteristics and Timing
Requirements”
Appendix A: “PIC32 Flash Memory Map”
Appendix B: “Hex File Format”
Appendix C: “Device IDs”
Appendix D: “Revision History”
When in development of a programming tool, it is
necessary to understand the internal Flash program
operations of the target device and the Special
Function Registers (SFRs) used to control Flash
programming, as these same operations and registers
are used by an external programming tool and its
software. These operations and control registers are
described in the
“Flash Program Memory”
chapter in
the specific device data sheet, and the related
“PIC32
Family Reference Manual”
section. It is highly
recommended that these documents be used in
conjunction with this programming specification.
An external tool programming setup consists of an
external programmer tool and a target PIC32 device.
Figure 2-1
illustrates a typical programming setup. The
programmer tool is responsible for executing
necessary programming steps and completing the
programming operation.
FIGURE 2-1:
PROGRAMMING SYSTEM
SETUP
Target PIC32 Device
External
Programmer
CPU
On-Chip Memory
2007-2017 Microchip Technology Inc.
DS60001145U-page 1
PIC32
2.1
Devices with Dual Flash Panel and
Dual Boot Regions
2.2
Programming Interfaces
All PIC32 devices provide two physical interfaces to the
external programmer tool:
• 2-wire In-Circuit Serial Programming™ (ICSP™)
• 4-wire Joint Test Action Group (JTAG)
See
Section 4.0 “Connecting to the Device”
for
more information.
Either of these methods may use a downloadable
Programming Executive (PE). The PE executes from
the target device RAM and hides device programming
details from the programmer. It also removes overhead
associated with data transfer and improves overall data
throughput. Microchip has developed a PE that is
available for use with any external programmer, see
Section 17.0 “The Programming Executive”
for
more information.
Section 3.0 “Programming Steps”
describes high-
level programming steps, followed by a brief
explanation of each step. Detailed explanations are
available in corresponding sections of this document.
More information on programming commands, EJTAG,
and DC specifications are available in the following
sections:
•
Section 19.0 “Configuration Memory and
Device ID”
•
Section 20.0 “TAP Controllers”
•
Section 21.0 “AC/DC Characteristics and
Timing Requirements”
The PIC32MKXXXXXXD/E/F/K/L/M and PIC32MZ
families of devices incorporate several features useful
for field (self) programming of the device. These
features include dual Flash panels with dual boot
regions, an aliasing scheme for the boot regions
allowing automatic selection of boot code at start-up
and a panel swap feature for Program Flash. The two
Flash panels and their associated boot regions can be
erased and programmed separately. Refer to the
Section
48.
“Memory
Organization
and
Permissions”
(DS60001214) of the
“PIC32 Family
Reference Manual”
for a detailed explanation of these
features.
A development tool used for production programming
will not be concerned about most of these features with
the following exceptions:
• Ensuring the SWAP bit (NVMCON<7>) is in the
proper setting. The default setting is ‘0’ for no swap
of panels. The development tool should assume the
default setting when generating source files for the
programming tool.
• Proper handling of the aliasing of the boot memory
in the checksum calculation. The aliased sections
will be duplicates of the fixed sections. See
Section 18.0 “Checksum”
for more information on
checksum calculations with aliased regions
• For PIC32MK devices, using the Erase/Retry
feature when an attempt to erase a Flash page fails
and needs to be retried. See
Section 13.0
“Initiating a Page Erase”
for more information.
2.3
Enhanced JTAG (EJTAG)
The 2-wire and 4-wire interfaces use the EJTAG
protocol to exchange data with the programmer. While
this document provides a working description of this
protocol as needed, advanced users are advised to
refer to the Imagination Technologies Limited web site
(www.imgtec.com) for more information.
2.4
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Data Sizes
Data sizes are defined as follows:
One word: 32 bits
One-half word: 16 bits
One-quarter word: 8 bits
One Byte: 8 bits
DS60001145U-page 2
2007-2017 Microchip Technology Inc.
PIC32
3.0
PROGRAMMING STEPS
All tool programmers must perform a common set of
steps, regardless of the actual method being used.
Figure 3-1
shows the set of steps to program PIC32
devices.
The following sequence lists the programming steps
with a brief explanation of each step. More detailed
information about these steps is available in the
subsequent sections.
1.
Connect to the target device.
To ensure successful programming, all required
pins must be connected to appropriate signals.
See
Section 4.0 “Connecting to the Device”
for more information.
2.
Place the target device in programming mode.
For 2-wire programming methods, the target
device must be placed in a special programming
mode (Enhanced ICSP™) before executing any
other steps.
Note:
For the 4-wire programming methods,
Step 2 is not applicable.
FIGURE 3-1:
PROGRAMMING FLOW
Start
Enter Enhanced ICSP™
(Only required for 2-wire)
Check Device Status
See
Section 7.0 “Entering 2-Wire Enhanced
ICSP Mode”
for more information.
3.
Check the status of the device.
Checks the status of the device to ensure it is
ready to receive information from the
programmer.
See
Section 8.0 “Check Device Status”
for
more information.
4.
Erase the target device.
If the target memory block in the device is not
blank, or if the device is code-protected, an
erase step must be performed before
programming any new data.
See
Section 9.0 “Erasing the Device”
for
more information.
Erase Device
Enter Serial Exec Mode
Download the PE
(Optional)
Download a Data Block
5.
Enter programming mode.
Verifies that the device is not code-protected
and boots the TAP controller to start sending
and receiving data to and from the PIC32 CPU.
Initiate Flash Write
See
Section 10.0 “Entering Serial Execution
Mode”
for more information.
No
Done
Yes
Verify Device
Exit Programming Mode
Done
2007-2017 Microchip Technology Inc.
DS60001145U-page 3
PIC32
6.
Download the Programming Executive (PE).
The PE is a small block of executable code that
is downloaded into the RAM of the target device.
It will receive and program the actual data.
Note:
If the programming method being used
does not require the PE, Step 6 is not
applicable.
See
Section 11.0
“Downloading
the
Programming Executive (PE)”
for more
information.
7.
Download the block of data to program.
All methods, with or without the PE, must
download the desired programming data into a
block of memory in RAM.
See
Section 12.0 “Downloading a Data
Block”
for more information.
8.
Initiate Flash Write.
After downloading each block of data into RAM,
the programming sequence must be started to
program it into the target device’s Flash
memory.
See
Section 14.0 “Initiating a Flash Row
Write”
for more information.
9.
Repeat Step 7 and Step 8 until all data blocks
are downloaded and programmed.
10. Verify the program memory.
After all programming data and Configuration
bits are programmed, the target device memory
should be read back and verified for the
matching content.
See
Section 15.0 “Verify Device Memory”
for
more information.
11. Exit the programming mode.
The newly programmed data is not effective until
either power is removed and reapplied to the
target device or an exit programming sequence
is performed.
See
Section 16.0 “Exiting
Mode”
for more information.
Programming
DS60001145U-page 4
2007-2017 Microchip Technology Inc.
PIC32
4.0
CONNECTING TO THE DEVICE
4.1
4-wire Interface
The PIC32 family provides two possible physical
interfaces for connecting and programming the
memory contents, see
Figure 4-1.
For all programming
interfaces, the target device must be powered and all
required signals must be connected. In addition, the
interface must be enabled, either through its
Configuration bit, as in the case of the JTAG 4-wire
interface, or though a special initialization sequence, as
is the case for the 2-wire ICSP interface.
The JTAG interface is enabled by default in blank
devices shipped from the factory.
Enabling ICSP is described in
Section 7.0 “Entering
2-Wire Enhanced ICSP Mode”.
One possible interface is the 4-wire JTAG (IEEE
1149.1) port.
Table 4-1
lists the required pin
connections. This interface uses the following four
communication lines to transfer data to and from the
PIC32 device being programmed:
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Test Clock Input (TCK)
Test Mode Select Input (TMS)
Test Data Input (TDI)
Test Data Output (TDO)
Refer to the specific device data sheet for the
connection of the signals to the device pins.
4.1.1
TEST CLOCK INPUT (TCK)
FIGURE 4-1:
PROGRAMMING
INTERFACES
2-wire
ICSP™
OR
PIC32
TCK is the clock that controls the updating of the TAP
controller and the shifting of data through the Instruc-
tion or selected Data registers. TCK is independent of
the processor clock with respect to both frequency and
phase.
4.1.2
TEST MODE SELECT INPUT (TMS)
Programmer
4-wire
JTAG
+
MCLR, V
DDCORE
(1)
, V
DDR1V8
(1)
,
V
DDIO
, V
SS
, V
SS1V8
(1)
TMS is the control signal for the TAP controller. This
signal is sampled on the rising edge of TCK.
4.1.3
TEST DATA INPUT (TDI)
Note 1:
This pin is not available on all devices.
Refer to the
“Pin Diagrams”
or
“Pin
Tables”
section in the specific device data
sheet to determine availability.
TDI is the test data input to the Instruction or selected
Data register. This signal is sampled on the rising edge
of TCK for some TAP controller states.
4.1.4
TEST DATA OUTPUT (TDO)
TDO is the test data output from the Instruction or Data
registers. This signal changes on the falling edge of
TCK. TDO is only driven when data is shifted out,
otherwise the TDO is tri-stated.
TABLE 4-1:
4-WIRE INTERFACE PINS
Device Pin Name
Pin
Type
Pin Description
I
Programming Enable
MCLR
(2)
ENVREG
I
Enable for On-Chip Voltage Regulator
(2)
, V
DDR1V8
(2)
, V
BAT
(2)
,
V
DD
, V
DD
IO
, V
DDCORE
P
Power Supply
(1)
and AV
DD
P
Ground
V
SS
, V
SS1V8
(2)
, and AV
SS
(1)
V
CAP
(2)
P
CPU logic filter capacitor connection
TDI
I
Test Data In
TDO
O
Test Data Out
TCK
I
Test Clock
TMS
I
Test Mode State
Legend:
I = Input
O = Output
P = Power
Note 1:
All power supply and ground pins must be connected, including analog supplies (AV
DD
) and ground (AV
SS
).
2:
This pin is not available on all devices. Refer to the
“Pin Diagrams”
or
“Pin Tables”
section in the specific
device data sheet to determine availability.
2007-2017 Microchip Technology Inc.
DS60001145U-page 5
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