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consumer and mobile devices. The new company “Cypress Semiconductor Corp.” will continue to offer “Spansion, Inc.” products
to new and existing customers.
CONTINUITY OF SPECIFICATIONS
There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made
are the result of normal document improvements and are noted in the document history page, where supported. Future revisions
will occur when appropriate, and changes will be noted in a document history page.
CONTINUITY OF ORDERING PART NUMBERS
Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part Numbers listed in
this document.
FOR MORE INFORMATION
Please visit our website at
www.cypress.com
or contact your
local sales office
for additional information about Cypress products
and services.
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ABOUT CYPRESS
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industrial, home automation and appliances, consumer electronics and medical products. Cypress’s programmable systems-on-
chip, general-purpose microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance
memories help engineers design differentiated products and get them to market first.
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Cypress Semiconductor Corporation
Document Number: 002-00648 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 15, 2017
S25FL129P
128-Mbit 3.0 V Flash Memory
This product is not recommended for new and current designs. For new and current designs, S25FL128S supersedes S25FL129P.
This is the factory-recommended migration path. Please refer to the S25FL128S data sheet for specifications and ordering
information.
Distinctive Characteristics
Architectural Advantages
Single power supply operation
– Full voltage range: 2.7 to 3.6V read and write operations
Memory architecture
– Uniform 64 KB sectors
– Top or bottom parameter block (Two 64-KB sectors broken down
into sixteen 4-KB sub-sectors each)
One time programmable (OTP) area for permanent, secure
identification; can be programmed and locked at the factory or by the
customer
CFI (Common Flash Interface) compliant: allows host system to
identify and accommodate multiple flash devices
Process technology
– Manufactured on 0.09 µm MirrorBit
®
process technology
Package option
– Industry Standard Pinouts
– 16-pin SO package (300 mils)
– 8-contact WSON package (6 x 8 mm)
– 24-ball BGA (6 x 8 mm) package, 5 x 5 pin configuration
– 24-ball BGA (6 x 8 mm) package, 6 x 4 pin configuration
– Uniform 256 KB sectors (no 4-KB sub-sectors)
– 256-byte page size
– Backward compatible with the S25FL128P (uniform 256 KB
sector) device
Program
– Page Program (up to 256 bytes) in 1.5 ms (typical)
– Program operations are on a page by page basis
– Accelerated programming mode via 9V W#/ACC pin
– Quad Page Programming
Erase
– Bulk erase function
– Sector erase (SE) command (D8h) for 64 KB and 256 KB sectors
– Sub-sector erase (P4E) command (20h) for 4 KB sectors
(for uniform 64-KB sector device only)
– Sub-sector erase (P8E) command (40h) for 8 KB sectors
(for uniform 64-KB sector device only)
Cycling endurance
– 100,000 cycles per sector typical
Data retention
– 20 years typical
Device ID
– JEDEC standard two-byte electronic signature
– RES command one-byte electronic signature for backward
compatibility
Performance Characteristics
Speed
– Normal READ (Serial): 40 MHz clock rate
– FAST_READ (Serial): 104 MHz clock rate (maximum)
– DUAL I/O FAST_READ: 80 MHz clock rate or
20 MB/s effective data rate
– QUAD I/O FAST_READ: 80 MHz clock rate or
40 MB/s effective data rate
Power saving standby mode
– Standby Mode 80 µA (typical)
– Deep Power-Down Mode 3 µA (typical)
Memory Protection Features
Memory protection
– W#/ACC pin works in conjunction with Status Register Bits to
protect specified memory areas
– Status Register Block Protection bits (BP2, BP1, BP0) in status
Cypress Semiconductor Corporation
Document Number: 002-00648 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 15, 2017
S25FL129P
General Description
The S25FL129P is a 3.0 Volt (2.7V to 3.6V), single-power-supply Flash memory device. The device is offered in two configurations:
256 uniform 64 KB sectors with the two (Top or Bottom) 64 KB sectors further split up into thirty-two 4 KB sub sectors, or 64 uniform
256 KB sectors. The S25FL129P device is backward compatible with the S25FL128P (uniform 256 KB sector) device.
The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are designed to be
programmed in-system with the standard system 3.0-volt V
CC
supply.
The S25FL129P device adds the following high-performance features using 5 new instructions:
Dual Output Read using both SI and SO pins as output pins at a clock rate of up to 80 MHz
Quad Output Read using SI, SO, W#/ACC and HOLD# pins as output pins at a clock rate of up to 80 MHz
Dual I/O High Performance Read using both SI and SO pins as input and output pins at a clock rate of up to 80 MHz
Quad I/O High Performance Read using SI, SO, W#/ACC and HOLD# pins as input and output pins at a clock rate of up to 80
MHz
Quad Page Programming using SI, SO, W#/ACC and HOLD# pins as input pins to program data at a clock rate of up to 80 MHz
The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device supports Sector Erase
and Bulk Erase commands.
Each device requires only a 3.0-volt power supply (2.7V to 3.6V) for both read and write functions. Internally generated and
regulated voltages are provided for the program operations. This device requires a high voltage supply to the W#/ACC pin to enable
the Accelerated Programming mode.
The S25FL129P device also offers a One-Time Programmable area (OTP) of up to 128-bits (16 bytes) for permanent secure
identification and an additional 490 bytes of OTP space for other use. This OTP area can be programmed or read using the OTPP or
OTPR instructions.
Document Number: 002-00648 Rev. *J
Page 3 of 66
S25FL129P
Contents
Distinctive Characteristics
.................................................. 2
General Description
............................................................. 3
1.
2.
3.
4.
5.
5.1
6.
7.
7.1
7.2
7.3
7.4
7.5
Block Diagram..............................................................
5
Connection Diagrams..................................................
5
Input/Output Descriptions...........................................
7
Logic Symbol
............................................................... 7
Ordering Information
................................................... 8
Valid Combinations ........................................................ 8
SPI Modes.....................................................................
9
10
10
10
10
10
10
10
11
11
13
14
14
20
22
23
24
25
26
28
29
33
34
34
35
36
37
9.14 Page Program (PP)....................................................... 39
9.15 QUAD Page Program (QPP) ........................................ 40
9.16 Parameter Sector Erase (P4E, P8E) (only applica-
ble for the uniform 64 KB sector device)....................... 41
9.17 Sector Erase (SE) ......................................................... 42
9.18 Bulk Erase (BE) ............................................................ 43
9.19 Deep Power-Down (DP) ............................................... 44
9.20 Release from Deep Power-Down (RES)....................... 45
9.21 Clear Status Register (CLSR)....................................... 46
9.22 OTP Program (OTPP)................................................... 47
9.23 Read OTP Data Bytes (OTPR) ..................................... 47
10.
10.1
10.2
10.3
11.
12.
13.
OTP Regions
............................................................... 48
Programming OTP Address Space............................... 48
Reading OTP Data ....................................................... 48
Locking OTP Regions................................................... 48
Power-up and Power-down........................................
51
Initial Delivery State....................................................
52
Program Acceleration via W#/ACC Pin.....................
52
Device Operations
.....................................................
Byte or Page Programming..........................................
Quad Page Programming ............................................
Dual and Quad I/O Mode .............................................
Sector Erase / Bulk Erase............................................
Monitoring Write Operations Using the Status Reg-
ister ..............................................................................
7.6 Active Power and Standby Power Modes....................
7.7 Status Register ............................................................
7.8 Configuration Register .................................................
7.9 Data Protection Modes ................................................
7.10 Hold Mode (HOLD#) ....................................................
7.11 Accelerated Programming Operation...........................
8.
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
Command Definitions................................................
Read Data Bytes (READ) ............................................
Read Data Bytes at Higher Speed (FAST_READ) ......
Dual Output Read Mode (DOR)...................................
Quad Output Read Mode (QOR) .................................
DUAL I/O High Performance Read Mode (DIOR)........
Quad I/O High Performance Read Mode (QIOR) ........
Read Identification (RDID) ...........................................
Read-ID (READ_ID).....................................................
Write Enable (WREN) ..................................................
Write Disable (WRDI)...................................................
Read Status Register (RDSR) .....................................
Read Configuration Register (RCR) ............................
Write Registers (WRR) ................................................
14. Electrical Specifications.............................................
54
14.1 Absolute Maximum Ratings .......................................... 54
15.
16.
17.
Operating Ranges
....................................................... 54
DC Characteristics......................................................
55
Test Conditions
........................................................... 56
Sector Address Table
................................................ 15
18. AC Characteristics......................................................
57
18.1 Capacitance .................................................................. 58
19. Physical Dimensions
.................................................. 60
19.1 SO3 016 — 16-pin Wide Plastic Small Outline
Package (300-mil Body Width) ..................................... 60
19.2 WSON 8-contact (6 x 8 mm) No-Lead Package
(WNF008) ..................................................................... 61
19.3 FAB024 — 24-ball Ball Grid Array (6 x 8 mm)
package ........................................................................ 62
19.4 FAC024 — 24-ball Ball Grid Array (6 x 8 mm)
package ........................................................................ 63
20.
Revision History..........................................................
64
Document Number: 002-00648 Rev. *J
Page 4 of 66
S25FL129P
1. Block Diagram
SRAM
PS
Array - L
Logic
X
D
E
C
Array - R
RD
DATA PATH
IO
CS#
SCK
SO / IO1
V
CC
HOLD# / IO3
W# / ACC / IO2
SI / IO0
GND
16
15
14
13
12
11
10
9
SCK
SI/IO0
DNC
DNC
DNC
DNC
GND
W#/ACC/IO2
2. Connection Diagrams
Figure 2.1
16-pin Plastic Small Outline Package (SO)
HOLD#/IO3
VCC
DNC
DNC
DNC
DNC
CS#
SO/IO1
1
2
3
4
5
6
7
8
Note
DNC = Do Not Connect (Reserved for future use)
Document Number: 002-00648 Rev. *J
Page 5 of 66
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