DSP56303AG100B1 datasheet, PDF

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DSP56303AG100B1: DescriptionDigital Signal Processors u0026 Controllers - DSP, DSC 24 BIT DSP PB FREE; Categorysemiconductor The embedded processor and controller; File Size1MB，108 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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Digital Signal Processors u0026 Controllers - DSP, DSC 24 BIT DSP PB FREE

DSP56303AG100B1 Parametric

Parameter Name	Attribute value
Product Category	Digital Signal Processors & Controllers - DSP, DSC
Manufacturer	NXP
Mounting Style	SMD/SMT
Package / Case	LQFP-144
Product	DSPs
Core	56300
Maximum Clock Frequency	100 MHz
Data RAM Size	24 kB
Operating Supply Voltage	3.3 V
Maximum Operating Temperature	+ 100 C
Data Bus Width	24 bit
Instruction Type	Fixed Point
Minimum Operating Temperature	- 40 C
Unit Weight	0.046530 oz

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Freescale Semiconductor

Technical Data

DSP56303

Rev. 11, 2/2005

DSP56303

24-Bit Digital Signal Processor

Memory Expansion Area

Triple

Timer

HI08

ESSI

SCI

PrograM

RAM

4096

bits

(default)

PM_EB

X Data

RAM

2048

bits

(default)

XM_EB

Y Data

RAM

2048

bits

(default)

YM_EB

Peripheral

Expansion Area

Address

Generation

Unit

Six-Channel

DMA Unit

Bootstrap

ROM

YAB

XAB

PAB

DAB

24-Bit

External

Address

Bus

Address

Switch

External

Bus

Interface

and Inst.

Cache Control

Control

External

Data Bus

Switch

The DSP56303 is intended

for use in telecommunication

applications, such as multi-

line voice/data/ fax

processing, video

conferencing, audio

applications, control, and

general digital signal

processing.

PIO_EB

DSP56300

Core

DDB

YDB

XDB

PDB

GDB

Internal

Data

Bus

Switch

EXTAL

XTAL

Clock

Generator

PLL

RESET

PINIT/NMI

Program

Interrupt

Controller

Program

Decode

Controller

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

Program

Address

Generator

What’s New?

Data

Rev. 11 includes the following

changes:

•

Adds lead-free packaging and

part numbers.

24 + 56

→

56-bit MAC

Two 56-bit Accumulators

56-bit Barrel Shifter

Data ALU

Power

Management

JTAG

OnCE™

Figure 1.

DSP56303 Block Diagram

The DSP56303 is a member of the DSP56300 core family of programmable CMOS DSPs. Significant architectural

features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The

DSP56303 offers 100 MMACS using an internal 100 MHz clock at 3.0–3.6 volts. The DSP56300 core family

offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power to enable

wireless, telecommunications, and multimedia products.

Table of Contents

Data Sheet Conventions .......................................................................................................................................ii

Features...............................................................................................................................................................iii

Target Applications ............................................................................................................................................. iv

Product Documentation ......................................................................................................................................iv

Chapter 1

Signals/Connections

1.1

1.2

1.3

1.5

1.6

1.7

1.8

1.9

1.10

1.11

1.12

Power ................................................................................................................................................................1-3

Ground ..............................................................................................................................................................1-3

Clock.................................................................................................................................................................1-4

External Memory Expansion Port (Port A) ......................................................................................................1-4

Interrupt and Mode Control ..............................................................................................................................1-7

Host Interface (HI08)........................................................................................................................................1-8

Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-11

Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-12

Serial Communication Interface (SCI) ...........................................................................................................1-14

Timers .............................................................................................................................................................1-15

JTAG and OnCE Interface ..............................................................................................................................1-16

Maximum Ratings.............................................................................................................................................2-1

Thermal Characteristics ....................................................................................................................................2-2

DC Electrical Characteristics............................................................................................................................2-2

AC Electrical Characteristics............................................................................................................................2-3

TQFP Package Description...............................................................................................................................3-2

TQFP Package Mechanical Drawing................................................................................................................3-9

MAP-BGA Package Description ....................................................................................................................3-10

MAP-BGA Package Mechanical Drawing .....................................................................................................3-18

Thermal Design Considerations........................................................................................................................4-1

Electrical Design Considerations......................................................................................................................4-2

Power Consumption Considerations.................................................................................................................4-3

PLL Performance Issues ...................................................................................................................................4-4

Input (EXTAL) Jitter Requirements .................................................................................................................4-5

Chapter 2

Specifications

2.1

2.3

2.4

2.5

Chapter 3

Packaging

3.1

3.2

3.3

3.4

Chapter 4

Design Considerations

4.1

4.2

4.3

4.4

4.5

Appendix A

Power Consumption Benchmark

Data Sheet Conventions

OVERBAR

“asserted”

“deasserted”

Examples:

Indicates a signal that is active when pulled low (For example, the

RESET

pin is active when

low.)

Means that a high true (active high) signal is high or that a low true (active low) signal is low

Means that a high true (active high) signal is low or that a low true (active low) signal is high

Signal/Symbol

Logic State

Voltage

Signal State

True

Asserted

False

Deasserted

True

Asserted

False

Deasserted

Note:

Values for

, and

are defined by individual product specifications.

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

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