2016.06.10
Cyclone V Device Overview
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The Cyclone
®
V devices are designed to simultaneously accommodate the shrinking power consumption,
cost, and time-to-market requirements; and the increasing bandwidth requirements for high-volume and
cost-sensitive applications.
Enhanced with integrated transceivers and hard memory controllers, the Cyclone V devices are suitable
for applications in the industrial, wireless and wireline, military, and automotive markets.
Cyclone V Device Handbook: Known Issues
Lists the planned updates to the Cyclone V Device Handbook chapters.
Related Information
Key Advantages of Cyclone V Devices
Table 1: Key Advantages of the Cyclone V Device Family
Advantage
Supporting Feature
Lower power consumption • Built on TSMC's 28 nm low-power (28LP) process technology and
includes an abundance of hard intellectual property (IP) blocks
• Up to 40% lower power consumption than the previous generation
device
Improved logic integration • 8-input adaptive logic module (ALM)
and differentiation capabil‐ • Up to 13.59 megabits (Mb) of embedded memory
ities
• Variable-precision digital signal processing (DSP) blocks
Increased bandwidth
capacity
Hard processor system
(HPS) with integrated
ARM
®
Cortex
™
-A9
MPCore processor
• 3.125 gigabits per second (Gbps) and 6.144 Gbps transceivers
• Hard memory controllers
• Tight integration of a dual-core ARM Cortex-A9 MPCore processor,
hard IP, and an FPGA in a single Cyclone V system-on-a-chip (SoC)
• Supports over 128 Gbps peak bandwidth with integrated data coherency
between the processor and the FPGA fabric
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trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html.
Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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9001:2008
Registered
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2
Summary of Cyclone V Features
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2016.06.10
Advantage
Supporting Feature
Lowest system cost
• Requires only two core voltages to operate
• Available in low-cost wirebond packaging
• Includes innovative features such as Configuration via Protocol (CvP)
and partial reconfiguration
Summary of Cyclone V Features
Table 2: Summary of Features for Cyclone V Devices
Feature
Description
Technology
Packaging
• TSMC's 28-nm low-power (28LP) process technology
• 1.1 V core voltage
• Wirebond low-halogen packages
• Multiple device densities with compatible package footprints for seamless
migration between different device densities
• RoHS-compliant and leaded
(1)
options
Enhanced 8-input ALM with four registers
• M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)
• Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can
use up to 25% of the ALMs as MLAB memory
Variable-precision
DSP
• Native support for up to three signal processing precision
levels (three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in
the same variable-precision DSP block
• 64-bit accumulator and cascade
• Embedded internal coefficient memory
• Preadder/subtractor for improved efficiency
DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC support
PCI Express
®
(PCIe
®
) Gen2 and Gen1 (x1, x2, or x4) hard IP
with multifunction support, endpoint, and root port
High-performance
FPGA fabric
Internal memory
blocks
Embedded Hard IP
blocks
Memory controller
Embedded
transceiver I/O
Clock networks
• Up to 550 MHz global clock network
• Global, quadrant, and peripheral clock networks
• Clock networks that are not used can be powered down to reduce dynamic power
(1)
Contact Altera for availability.
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Summary of Cyclone V Features
3
Feature
Description
Phase-locked loops
(PLLs)
FPGA General-
purpose I/Os
(GPIOs)
• Precision clock synthesis, clock delay compensation, and zero delay buffering
(ZDB)
• Integer mode and fractional mode
•
•
•
•
875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS transmitter
400 MHz/800 Mbps external memory interface
On-chip termination (OCT)
3.3 V support with up to 16 mA drive strength
Low-power high-
• 614 Mbps to 6.144 Gbps integrated transceiver speed
speed serial interface • Transmit pre-emphasis and receiver equalization
• Dynamic partial reconfiguration of individual channels
• Single or dual-core ARM Cortex-A9 MPCore processor-up to 925 MHz maximum
frequency with support for symmetric and asymmetric multiprocessing
( Cyclone V SE, SX,
and ST devices only) • Interface peripherals—10/100/1000 Ethernet media access control (EMAC),
USB 2.0 On-The-GO (OTG) controller, quad serial peripheral interface (QSPI)
flash controller, NAND flash controller, Secure Digital/MultiMediaCard (SD/
MMC) controller, UART, controller area network (CAN), serial peripheral
interface (SPI), I
2
C interface, and up to 85 HPS GPIO interfaces
• System peripherals—general-purpose timers, watchdog timers, direct memory
access (DMA) controller, FPGA configuration manager, and clock and reset
managers
• On-chip RAM and boot ROM
• HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight
HPS-to-FPGA bridges that allow the FPGA fabric to issue transactions to slaves in
the HPS, and vice versa
• FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to
the multiport front end (MPFE) of the HPS SDRAM controller
• ARM CoreSight
™
JTAG debug access port, trace port, and on-chip trace storage
Configuration
• Tamper protection—comprehensive design protection to protect your valuable IP
investments
• Enhanced advanced encryption standard (AES) design security features
• CvP
• Dynamic reconfiguration of the FPGA
• Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel
(FPP) x8 and x16 configuration options
• Internal scrubbing
(2)
• Partial reconfiguration
(3)
HPS
(2)
The SEU internal scrubbing feature is available for Cyclone V E, GX, SE, and SX devices with the "SC"
suffix in the part number. For device availability and ordering, contact your local Altera sales representa‐
tives.
Altera Corporation
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Cyclone V Device Variants and Packages
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Cyclone V Device Variants and Packages
Table 3: Device Variants for the Cyclone V Device Family
Variant
Description
Cyclone V E
Cyclone V GX
Cyclone V GT
Cyclone V SE
Cyclone V SX
Cyclone V ST
Optimized for the lowest system cost and power requirement for a wide spectrum of
general logic and DSP applications
Optimized for the lowest cost and power requirement for 614 Mbps to 3.125 Gbps
transceiver applications
The FPGA industry’s lowest cost and lowest power requirement for 6.144 Gbps
transceiver applications
SoC with integrated ARM-based HPS
SoC with integrated ARM-based HPS and 3.125 Gbps transceivers
SoC with integrated ARM-based HPS and 6.144 Gbps transceivers
Cyclone V E
This section provides the available options, maximum resource counts, and package plan for the
Cyclone V E devices.
The information in this section is correct at the time of publication. For the latest information and to get
more details, refer to the Altera Product Selector.
Related Information
Altera Product Selector
Provides the latest information about Altera products.
(3)
The partial reconfiguration feature is available for Cyclone V E, GX, SE, and SX devices with the "SC"
suffix in the part number. For device availability and ordering, contact your local Altera sales representa‐
tives.
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Available Options
5
Available Options
Figure 1: Sample Ordering Code and Available Options for Cyclone V E Devices
The SEU internal scrubbing feature is available for Cyclone V E, GX, SE, and SX devices with the "SC"
suffix in the part number. For device availability and ordering, contact your local Altera sales
representatives.
Embedded Hard IPs
B : No hard PCIe or hard
memory controller
F : No hard PCIe and maximum
2 hard memory controllers
Family Signature
5C : Cyclone V
Package Type
F : FineLine BGA (FBGA)
U : Ultra FineLine BGA (UBGA)
M : Micro FineLine BGA (MBGA)
Operating Temperature
C : Commercial (T
J
= 0° C to 85° C)
I : Industrial (T
J
= -40° C to 100° C)
A : Automotive (T
J
= -40° C to 125° C)
5C
E
F
A9
F
31
C
7
N
Family Variant
E : Enhanced logic/memory
Member Code
A2 : 25K logic elements
A4 : 49K logic elements
A5 : 77K logic elements
A7 : 150K logic elements
A9 : 301K logic elements
Package Code
FBGA Package Type
17 : 256 pins
23 : 484 pins
27 : 672 pins
31 : 896 pins
UBGA Package Type
15 : 324 pins
19 : 484 pins
MBGA Package Type
13 : 383 pins
15 : 484 pins
Optional Suffix
Indicates specific device
options or shipment method
N : Lead-free packaging
Contact Altera for availability
of leaded options
ES : Engineering sample
SC : Internal scrubbing support
FPGA Fabric Speed Grade
6 (fastest)
7
8
Maximum Resources
Table 4: Maximum Resource Counts for Cyclone V E Devices
Resource
Member Code
A2
A4
A5
A7
A9
Logic Elements (LE) (K)
ALM
Register
Memory
(Kb)
M10K
MLAB
25
9,434
37,736
1,760
196
25
50
4
49
18,480
73,920
3,080
303
66
132
4
77
29,080
116,320
4,460
424
150
300
6
150
56,480
225,920
6,860
836
156
312
7
301
113,560
454,240
12,200
1,717
342
684
8
Variable-precision DSP
Block
18 x 18 Multiplier
PLL
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