Integrated
Circuit
Systems, Inc.
ICS954204
Programmable Timing Control Hub™ for Mobile P4™ Systems
Recommended Application:
CK410M Compliant Main Clock with Integrated LCD Spread
Spectrum Clock.
Output Features:
•
2 - 0.7V current-mode differential CPU pairs
•
5 - 0.7V current-mode differential SRC pair for SATA and
PCI-E
•
1 - 0.7V current-mode differential CPU/SRC selectable
pair
•
4 - PCI (33MHz)
•
2 - PCICLK_F, (33MHz) free-running
•
1 - USB, 48MHz
•
1 - DOT, 96MHz, 0.7V current differential pair
•
1 - REF, 14.318MHz
•
1 - 0.7V current-mode differential LCD/SRC selectable
pair.
Key Specifications:
•
CPU outputs cycle-cycle jitter < 85ps
•
SRC outputs cycle-cycle jitter < 125ps
•
PCI outputs cycle-cycle jitter < 500ps
•
+/- 300ppm frequency accuracy on CPU & SRC clocks
•
+/- 100ppm frequency accuracy on USB clocks
Features/Benefits:
•
Supports tight ppm accuracy clocks for Serial-ATA and
SRC
•
Supports programmable spread percentage and
frequency
•
•
•
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Supports undriven differential CPU, SRC pair in PD#
for power management.
CLKREQ pins to support SRC power management.
Pin Configuration
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
ITP_EN/PCICLK_F0
*SELSRC_LCDCLK#/PCICLK_F1
Vtt_PwrGd#/PD
VDD48
FS
L
A/USB_48MHz
GND
DOTT_96MHz
DOTC_96MHz
FS
L
B/TEST_MODE
LCDCLK_SST/SRCCLKT0
LCDCLK_SSC/SRCCLKC0
SRCCLKT1
SRCCLKC1
VDDSRC
SRCCLKT2
SRCCLKC2
SRCCLKT3
SRCCLKC3
SRCCLKT4_SATA
SRCCLKC4_SATA
VDDSRC
Functionality
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCICLK2
PCI/SRC_STOP#
CPU_STOP#
FS
L
C/TEST_SEL
REFOUT
GND
X1
X2
VDDREF
SDATA
SCLK
GND
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
FS_C FS_B FS_A
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CPU
MHz
266.67
133.33
200.00
166.67
333.33
100.00
400.00
200.00
SRC
MHz
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
REF
MHz
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
U
SB
MHz
48.00
48.00
48.00
48.00
48.00
48.00
48.00
48.00
DOT
MHz
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
ICS954204
1. FS_C is a three-level input. Please see V
IL_FS
and V
IH_FS
specifications in the
Input/Supply/Common Output Parameters Table for correct values. Also refer
to the Test Clarification Table.
2. FS_B and FS_A are low-threshold inputs. Please see the V
IL_FS
and V
IH_FS
CPUCLKC1
specifications in the Input/Supply/Common Output Parameters Table for
IREF
correct values.
GNDA
VDDA
CPUCLKT2_ITP/SRCCLKT7
CPUCLKC2_ITP/SRCCLKC7
VDDSRC
CLKREQA#*
CLKREQB#*
SRCCLKT5
SRCCLKC5
GND
56-pin TSSOP
*100Kohm Pull-Up Resistor
0933D—03/16/05
Integrated
Circuit
Systems, Inc.
ICS954204
Pin Description
PIN # PIN NAME
1
2
3
4
5
6
7
8
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
ITP_EN/PCICLK_F0
PIN TYPE DESCRIPTION
PWR
PWR
OUT
OUT
OUT
PWR
PWR
I/O
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
0 = SRC pair
Latched input select for LCD_ss/ SRCCLK output frequency:
0 = LCD,
1 = SRCCLK/ 3.3V free-running PCI clock output.
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin used
to put the device into a low power state. The internal clocks, PLLs and the
crystal oscillator are stopped.
Power pin for the 48MHz output.3.3V
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock
output. 3.3V.
Ground pin.
True clock of differential pair for 96.00MHz DOT clock.
Complement clock of differential pair for 96.00MHz DOT clock.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode.
Refer to Test Clarification Table.
True clock of LCDCLK_SS output / True clock of SRCCLK differential pair.
Selected by SEL_LCDCLK#
Complementary clock of LCDCLK_SS output / Complementary clock of
SRCCLK differential pair. Selected by SEL_LCDCLK#
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC/SATA pair.
Complement clock of differential SRC/SATA pair.
Supply for SRC clocks, 3.3V nominal
9
*SELSRC_LCDCLK#/PCICLK_F1
I/O
10
11
12
13
14
15
16
Vtt_PwrGd#/PD
VDD48
FSLA/USB_48MHz
GND
DOTT_96MHz
DOTC_96MHz
FSLB/TEST_MODE
IN
PWR
I/O
PWR
OUT
OUT
IN
17
18
19
20
21
22
23
24
25
26
27
28
LCDCLK_SST/SRCCLKT0
LCDCLK_SSC/SRCCLKC0
SRCCLKT1
SRCCLKC1
VDDSRC
SRCCLKT2
SRCCLKC2
SRCCLKT3
SRCCLKC3
SRCCLKT4_SATA
SRCCLKC4_SATA
VDDSRC
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
0933D—03/16/05
2
Integrated
Circuit
Systems, Inc.
ICS954204
Pin Description (Continued)
PIN # PIN NAME
29
30
31
32
GND
SRCCLKC5
SRCCLKT5
CLKREQB#*
Type
PWR
OUT
OUT
IN
Pin Description
Ground pin.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs
are controlled.
0 = enabled, 1 = tri-stated
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs
are controlled.
0 = enabled, 1 = tri-stated
Supply for SRC clocks, 3.3V nominal
Complementary clock of CPU_ITP/SRC differential pair CPU_ITP/SRC
output. These are current mode outputs. External resistors are required for
voltage bias. Selected by ITP_EN input.
True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These
are current mode outputs. External resistors are required for voltage bias.
Selected by ITP_EN input.
3.3V power for the PLL core.
Ground pin for the PLL core.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Ground pin.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin.
Reference Clock output
3.3V tolerant input for CPU frequency selection. Low voltage threshold
inputs, see input electrical characteristics for Vil_FS and Vih_FS values.
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table
Stops all CPUCLK, except those set to be free running clocks
Stops all PCICLKs and SRCCLKs besides the free-running clocks at logic 0
level, when input low
PCI clock output.
33
34
35
CLKREQA#*
VDDSRC
CPUCLKC2_ITP/SRCCLKC7
IN
PWR
OUT
36
37
38
39
CPUCLKT2_ITP/SRCCLKT7
VDDA
GNDA
IREF
OUT
PWR
PWR
IN
40
41
42
43
44
45
46
47
48
49
50
51
52
CPUCLKC1
CPUCLKT1
VDDCPU
CPUCLKC0
CPUCLKT0
GND
SCLK
SDATA
VDDREF
X2
X1
GND
REFOUT
OUT
OUT
PWR
OUT
OUT
PWR
IN
I/O
PWR
OUT
IN
PWR
OUT
53
FSLC/TEST_SEL
IN
54
55
CPU_STOP#
PCI/SRC_STOP#
IN
IN
OUT
56
PCICLK2
*Pins 32 and 33 have pull-ups.
0933D—03/16/05
3
Integrated
Circuit
Systems, Inc.
ICS954204
General Description
ICS954204
is a CK410M Compliant clock synthesizer.
ICS954204
provides a single-chip solution for mobile systems built
with Intel P4-M processors and Intel mobile chipsets.
ICS954204
is driven with a 14.318MHz crystal and generates CPU
outputs up to 400MHz. It provides the tight ppm accuracy required by Serial ATA and PCI-Express.
Block Diagram
REFOUT
USB_48MHz
X1
X2
XTAL
OSC.
FIXED PLL
DIVIDER
DOT_96MHz
PCICLK(5:2)
PCICLK_F(1:0)
PROG.
SPREAD
MAIN PLL
SRCCLK(5:1)
PROG.
DIVIDERS
CPUCLK2_ITP/SRCCLK7
CPUCLK(1:0)
PCI/SRC_STOP#
CPU_STOP#
FSL(C:A)
ITP_EN
TEST_MODE
VTT_PWRGD#/PD
CLKREQ#A/B
SDATA
SCLK
SelSRC/LCDCLK#
CONTROL
LOGIC
LCDCLKSS/SRCCLK0
IREF
0933D—03/16/05
4
Integrated
Circuit
Systems, Inc.
ICS954204
General SMBus serial interface information for the ICS954204
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address D3
(H)
RD
ReaD
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
ACK
Byte N + X - 1
N
P
Not acknowledge
stoP bit
0933D—03/16/05
5
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