KSZ8794CNX
Integrated 4-Port 10/100 Managed Ethernet
Switch with Gigabit RGMII/MII/RMII Interface
Target Applications
• Industrial Ethernet Applications that Employ IEEE
802.3-Compliant MACs. (Ethernet/IP, Profinet,
MODBUS TCP, etc.)
• VoIP Phone
• Set-Top/Game Box
• Automotive
• Industrial Control
• IPTV POF
• SOHO Residential Gateway with Full-Wire Speed
of Four LAN Ports
• Broadband Gateway/Firewall/VPN
• Integrated DSL/Cable Modem
• Wireless LAN Access Point + Gateway
• Standalone 10/100 Switch
• Networked Measurement and Control Systems
- On-Chip Termination Resistors and Internal
Biasing for Differential Pairs to Reduce
Power
- HP Auto MDI/MDI-X Crossover Support Elim-
inates the Need to Differentiate Between
Straight or Crossover Cables in Applications
• MAC and GMAC Ports
- Three Internal Media Access Control (MAC1
to MAC3) Units and One Internal Gigabit
Media Access Control (GMAC4) Unit
- RGMII, MII, or RMII Interfaces Support for
the Port 4 GMAC4 with Uplink
- 2 KByte Jumbo Packet Support
- Tail Tagging Mode (One Byte Added Before
FCS) Support on Port 4 to Inform the Proces-
sor in which Ingress Port Receives the
Packet and its Priority
- Supports Reduced Media Independent Inter-
face (RMII) with 50 MHz Reference Clock
Output
- Supports Media Independent Interface (MII)
in Either PHY Mode or MAC Mode on Port 4
- LinkMD
®
Cable Diagnostic Capabilities for
Determining Cable Opens, Shorts, and
Length
• Advanced Switch Capabilities
- Non-Blocking Store-and-Forward Switch
Fabric Assures Fast Packet Delivery by Uti-
lizing a 1024-Entries Forwarding Table
- 64 KB Frame Buffer RAM
- IEEE 802.1q VLAN Support for up to 128
Active VLAN Groups (Full-Range 4096 of
VLAN IDs)
- IEEE 802.1p/Q Tag Insertion or Removal on
a Per Port Basis (Egress)
- VLAN ID Tag/Untag Options on Per Port
Basis
- Fully Compliant with IEEE 802.3/802.3u
Standards
- IEEE 802.3x Full-Duplex with Force-Mode
Option and Half-Duplex Back-Pressure Colli-
sion Flow Control
- IEEE 802.1w Rapid Spanning Tree Protocol
Support
- IGMP v1/v2/v3 Snooping for Multicast Packet
Filtering
Features
• Management Capabilities
- The KSZ8794CNX Includes All the Functions
of a 10/100BASE-T/TX Switch System Which
Combines a Switch Engine, Frame Buffer
Management, Address Look-Up Table,
Queue Management, MIB Counters, Media
Access Controllers (MAC), and PHY Trans-
ceivers
- Non-Blocking Store-and-Forward Switch
Fabric Assures Fast Packet Delivery by Uti-
lizing a 1024-Entries Forwarding Table
- Port Mirroring/Monitoring/Sniffing: Ingress
and/or Egress Traffic to Any Port
- MIB Counters for Fully Compliant Statistics
Gathering (36 Counters per Port)
- Support Hardware for Port-Based Flush and
Freeze Command in MIB Counter.
- Multiple Loopback of Remote PHY, and MAC
Modes Support for the Diagnostics
- Rapid Spanning Tree Support (RSTP) for
Topology Management and Ring/Linear
Recovery
• Robust PHY Ports
- Four Integrated IEEE 802.3/802.3u-Compli-
ant Ethernet Transceivers Supporting
10BASE-T and 100BASE-TX
- IEEE 802.1az EEE Supported
2016 Microchip Technology Inc.
DS00002134A-page 1
KSZ8794CNX
- QoS/CoS Packets Prioritization Support:
802.1p, DiffServ-Based and Re-Mapping of
802.1p Priority Field Per Port Basis on Four
Priority Levels
- IPv4/IPv6 QoS Support
- IPv6 Multicast Listener Discovery (MLD)
Snooping
- Programmable Rate Limiting at the Ingress
and Egress Ports on a Per Port Basis
- Jitter-Free Per Packet Based Rate Limiting
Support
- Tail Tag Mode (1 byte Added before FCS)
Support on Port 4 to Inform the Processor
which Ingress Port Receives the Packet
- Broadcast Storm Protection with Percentage
Control (Global and Per Port Basis)
- 1K Entry Forwarding Table with 64 KB Frame
Buffer
- 4 Priority Queues with Dynamic Packet Map-
ping for IEEE 802.1P, IPv4 TOS (DIFF-
SERV), IPv6 Traffic Class, etc.
- Supports WoL Using AMD’s Magic Packet
- VLAN and Address Filtering
- Supports 802.1x Port-Based Security,
Authentication and MAC-Based Authentica-
tion via Access Control Lists (ACL)
- Provides Port-Based and Rule-Based ACLs
to Support Layer 2 MAC SA/DA Address,
Layer 3 IP Address and IP Mask, Layer 4
TCP/UDP Port Number, IP Protocol, TCP
Flag and Compensation for the Port Security
Filtering
- Ingress and Egress Rate Limit Based on Bit
per Second (bps) and Packet-Based Rate
Limiting (pps)
• Configuration Registers Access
- High-Speed SPI (4-Wire, up to 50 MHz) Inter-
face to Access All Internal Registers
- MII Management (MIIM, MDC/MDIO 2-Wire)
Interface to Access All PHY Registers per
Clause 22.2.4.5 of the IEEE 802.3 Specifica-
tion
- I/O Pin Strapping Facility to Set Certain Reg-
ister Bits from I/O Pins During Reset Time
- Control Registers Configurable On-the-Fly
• Power and Power Management
- Full-Chip Software Power-Down (All Register
Values are Not Saved and Strap-In Value Will
Re-Strap After it Releases the Power-Down)
- Per-Port Software Power-Down
- Energy Detect Power-Down (EDPD), which
Disables the PHY Transceiver When Cables
are Removed
- Supports IEEE P802.3az Energy Efficient
Ethernet (EEE) to Reduce Power Consump-
tion in Transceivers in LPI State Even
Though Cables are Not Removed
- Dynamic Clock Tree Control to Reduce
Clocking in Areas that are Not in Use
- Low Power Consumption without Extra
Power Consumption on Transformers
- Voltages: Using External LDO Power Sup-
plies
- Analog V
DDAT
3.3V or 2.5V
- V
DDIO
Support 3.3V, 2.5V, and 1.8V
- Low 1.2V Voltage for Analog and Digital Core
Power
- WoL Support with Configurable Packet Con-
trol
• Additional Features
- Single 25 MHz ±50 ppm Reference Clock
Requirement
- Comprehensive Programmable Two-LED
Indicator Support for Link, Activity, Full-/Half-
Duplex, and 10/100 Speed
• Packaging and Environmental
- Commercial Temperature Range: 0°C to
+70°C
- Industrial Temperature Range: –40°C to
+85°C
- Small Package Available in a Lead-Free,
RoHS-Compliant 64-Pin QFN
- 0.065 µm CMOS Technology for Lower
Power Consumption
2016 Microchip Technology Inc.
DS00002134A-page 2
KSZ8794CNX
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
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2016 Microchip Technology Inc.
DS00002134A-page 3
KSZ8794CNX
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 5
2.0 Pin Description and Configuration ................................................................................................................................................... 6
3.0 Functional Description ................................................................................................................................................................... 12
4.0 Device Registers ........................................................................................................................................................................... 43
5.0 Operational Characteristics ......................................................................................................................................................... 106
6.0 Electrical Characteristics ............................................................................................................................................................. 107
7.0 Timing Diagrams .......................................................................................................................................................................... 109
8.0 Reset Circuit................................................................................................................................................................................. 117
9.0 Selection of Isolation Transformer ............................................................................................................................................... 118
10.0 Selection of Reference Crystal................................................................................................................................................... 118
11.0 Package Outlines ....................................................................................................................................................................... 119
Appendix A: Data Sheet Revision History ......................................................................................................................................... 120
The Microchip Web Site .................................................................................................................................................................... 121
Customer Change Notification Service ............................................................................................................................................. 121
Customer Support ............................................................................................................................................................................. 121
Product Identification System ............................................................................................................................................................ 122
DS00002134A-page 4
2016 Microchip Technology Inc.
KSZ8794CNX
1.0
1.1
INTRODUCTION
General Description
The KSZ8794CNX is a highly integrated, Layer 2-managed, four-port switch with numerous features designed to reduce
system cost. It is intended for cost-sensitive applications requiring three 10/100 Mbps copper ports and one 10/100/
1000 Mbps Gigabit uplink port. The KSZ8794CNX incorporates a small package outline, lowest power consumption with
internal biasing, and on-chip termination. Its extensive features set includes enhanced power management, program-
mable rate limiting and priority ratio, tagged and port-based VLAN, port-based security and ACL rule-based packet fil-
tering technology, QoS priority with four queues, management interfaces, enhanced MIB counters, high-performance
memory bandwidth, and a shared memory-based switch fabric with non-blocking support. The KSZ8794CNX provides
support for multiple CPU data interfaces to effectively address both current and emerging fast Ethernet and Gigabit
Ethernet applications where the GMAC interface can be configured to any of RGMII, MII, and RMII modes. The
KSZ8794CNX is built on the latest industry-leading Ethernet analog and digital technology, with features designed to
offload host processing and streamline the overall design:
• Three integrated 10/100BASE-T/TX MAC/PHYs.
• One integrated 10/100/1000BASE-T/TX GMAC with selectable RGMII, MII, or RMII interfaces.
• Small 64-pin QFN package.
A robust assortment of power management features including Energy Efficient Ethernet (EEE), PME, and WoL have
been designed in to satisfy energy efficient environments.
All registers in the MAC and PHY units can be managed through the SPI interface. MIIM PHY registers can be accessed
through the MDC/MDIO interface.
FIGURE 1-1:
FUNCTIONAL BLOCK DIAGRAM
KSZ8794
AUTO MDI/MDIX
10/100
T/TX
EEE PHY1
10/100
MAC 1
FIFO, FLOW CONTROL, VLAN TAGGING, PRIORITY
LOOK UP ENGINE
AUTO MDI/MDIX
10/100
T/TX
EEE PHY2
10/100
MAC 2
QUEUE MANAGEMENT
AUTO MDI/MDIX
10/100
T/TX
EEE PHY3
10/100
MAC 3
BUFFER MANAGEMENT
SW4-RGMII/MII/RMII
MDC, MDI/O FOR MIIM
CONTROL REG SPI I/F
10/100/1000
GMAC 4
FRAME BUFFER
SPI
LED0 {3:1]
LED1 {3:1]
LED I/F
CONTROL
REGISTERS
MIB COUNTERS
2016 Microchip Technology Inc.
DS00002134A-page 5
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