®
HI5805
Data Sheet
March 31, 2005
FN3984.7
12-Bit, 5MSPS A/D Converter
The HI5805 is a monolithic, 12-bit, Analog-to-Digital
Converter fabricated in Intersil’s HBC10 BiCMOS process. It
is designed for high speed, high resolution applications
where wide bandwidth and low power consumption are
essential.
The HI5805 is designed in a fully differential pipelined
architecture with a front end differential-in-differential-out
sample-and-hold (S/H). The HI5805 has excellent dynamic
performance while consuming 300mW power at 5MSPS.
The 100MHz full power input bandwidth is ideal for
communication systems and document scanner
applications. Data output latches are provided which present
valid data to the output bus with a latency of 3 clock cycles.
The digital outputs have a separate supply pin which can be
powered from a 3.0V to 5.0V supply.
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MSPS
• Low Power
• Internal Sample and Hold
• Fully Differential Architecture
• Full Power Input Bandwidth . . . . . . . . . . . . . . . . . 100MHz
• Low Distortion
• Internal Voltage Reference
• TTL/CMOS Compatible Digital I/O
• Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 3.0V
• Pb-Free Available (RoHS Compliant)
Applications
• Digital Communication Systems
• Undersampling Digital IF
• Document Scanners
• Additional Reference Documents
- AN9214 Using Intersil High Speed A/D Converters
- AN9707 Using the HI5805EVAL1 Evaluation Board
Ordering Information
PART
NUMBER
HI5805BIB
HI5805BIBZ
(See Note)
HI5805EVAL1
SAMPLE
RATE
5MSPS
5MSPS
TEMP.
RANGE (
o
C)
-40 to 85
-40 to 85
25
PACKAGE
PKG.
DWG. #
28 Ld SOIC (W) M28.3
28 Ld SOIC (W) M28.3
(Pb-free)
Evaluation Board
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
HI5805
(SOIC)
TOP VIEW
CLK 1
DV
CC1
2
D
GND1
3
DV
CC1
4
D
GND1
5
AV
CC
6
A
GND
7
V
IN+
8
V
IN-
9
V
DC
10
V
ROUT
11
V
RIN
12
A
GND
13
AV
CC
14
28 D0
27 D1
26 D2
25 D3
24 D4
23 D5
22 DV
CC2
21 D
GND2
20 D6
19 D7
18 D8
17 D9
16 D10
15 D11
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI5805
Functional Block Diagram
V
DC
V
IN
-
V
IN
+
S/H
STAGE 1
DV
CC2
BIAS
CLOCK
REF
CLK
V
ROUT
V
RIN
4-BIT
FLASH
+
4-BIT
DAC
∑
-
X8
DIGITAL DELAY
AND
DIGITAL ERROR CORRECTION
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
STAGE 3
4-BIT
FLASH
+
4-BIT
DAC
∑
X8
-
STAGE 4
4-BIT
FLASH
D
GND2
AV
CC
A
GND
DV
CC1
D
GND1
Typical Application Schematic
(LSB) (28) D0
(27) D1
V
ROUT
(11) (26) D2
(25) D3
V
RIN
(12)
(24) D4
A
GND
(7)
(23) D5
A
GND
(13)
(20) D6
D
GND1
(3)
(19) D7
D
GND1
(5)
(18) D8
D
GND2
(21)
(17) D9
(16) D10
(MSB) (15) D11
V
IN
+
V
IN
+ (8)
V
DC
(10)
V
IN
-
CLOCK
V
IN
- (9)
CLK (1)
(4) DV
CC1
(2) DV
CC1
(22) DV
CC2
0.1µF
(6) AV
CC
(14) AV
CC
HI5805
0.1µF
+5V
+
10µF
+
10µF
+5V
10µF AND 0.1µF CAPS ARE PLACED
AS CLOSE TO PART AS POSSIBLE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D
GND
A
GND
BNC
2
HI5805
Absolute Maximum Ratings
Supply Voltage, AV
CC
or DV
CC
to A
GND
or D
GND
. . . . . . . . . +6.0V
D
GND
to A
GND
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D
GND
to DV
CC
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A
GND
to AV
CC
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
Operating Conditions
Temperature Range, HI5805BIB . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AV
CC
= DV
CC1
= DV
CC2
= DV
CC3
= +5.0V, f
S
= 5MSPS at 50% Duty Cycle, V
RIN
= 3.5V, C
L
= 10pF,
T
A
= -40
o
C to 85
o
C, Differential Analog Input, Typical Values are Test Results at 25
o
C,
Unless Otherwise Specified
HI5805BIB (-40
o
C TO 85
o
C)
PARAMETER
ACCURACY
Resolution
Integral Linearity Error, INL
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
Offset Error, V
OS
Full Scale Error, FSE
DYNAMIC CHARACTERISTICS
Minimum Conversion Rate
Maximum Conversion Rate
Effective Number of Bits, ENOB
Signal to Noise and Distortion Ratio, SINAD
RMS Signal
=
-------------------------------------------------------------
-
RMS Noise + Distortion
Signal to Noise Ratio, SNR
RMS Signal
=
------------------------------
-
RMS Noise
Total Harmonic Distortion, THD
2nd Harmonic Distortion
3rd Harmonic Distortion
Spurious Free Dynamic Range, SFDR
Intermodulation Distortion, IMD
Transient Response
Over-Voltage Recovery
ANALOG INPUT
Maximum Peak-to-Peak Differential Analog Input Range
(V
IN
+ - V
IN
-)
Maximum Peak-to-Peak Single-Ended Analog Input Range
Analog Input Resistance, R
IN
Analog Input Capacitance, C
IN
Analog Input Bias Current, I
B
+ or I
B
-
Differential Analog Input Bias Current I
B DIFF
= (I
B
+ - I
B
-)
Full Power Input Bandwidth, FPBW
TEST CONDITION
MIN
12
TYP
-
±1
±0.5
19
32
0.5
-
11
68
MAX
-
±2
±1
-
-
-
-
-
-
UNITS
Bits
LSB
LSB
LSB
LSB
MSPS
MSPS
Bits
dB
f
IN
= DC
f
IN
= DC
f
IN
= DC
f
IN
= DC
No Missing Codes
No Missing Codes
f
IN
= 1MHz
f
IN
= 1MHz
-
-
-
-
-
5
10.0
-
f
IN
= 1MHz
-
68
-
dB
f
IN
= 1MHz
f
IN
= 1MHz
f
IN
= 1MHz
f
IN
= 1MHz
f
1
= 1MHz, f
2
= 1.02MHz
0.2V Overdrive
-
-
-
-
-
-
-
-
-
-80
-86
-83
83
-68
1
2
±2.0
4.0
-
10
-
±0.5
100
-
-
-
-
-
-
-
-
-
-
+10
-
-
dBc
dBc
dBc
dBc
dBc
Cycle
Cycle
V
V
MΩ
pF
µA
µA
MHz
(Notes 2, 3)
(Note 3)
1
-
-10
-
-
3
HI5805
Electrical Specifications
AV
CC
= DV
CC1
= DV
CC2
= DV
CC3
= +5.0V, f
S
= 5MSPS at 50% Duty Cycle, V
RIN
= 3.5V, C
L
= 10pF,
T
A
= -40
o
C to 85
o
C, Differential Analog Input, Typical Values are Test Results at 25
o
C,
Unless Otherwise Specified
(Continued)
HI5805BIB (-40
o
C TO 85
o
C)
PARAMETER
Analog Input Common Mode Voltage Range (V
IN
+ + V
IN
-) / 2
INTERNAL VOLTAGE REFERENCE
Reference Output Voltage, V
ROUT
(Loaded)
Reference Output Current
Reference Temperature Coefficient
REFERENCE VOLTAGE INPUT
Reference Voltage Input, V
RIN
Total Reference Resistance, R
L
Reference Current
DC BIAS VOLTAGE
DC Bias Voltage Output, V
DC
Max Output Current (Not To Exceed)
DIGITAL INPUTS (CLK)
Input Logic High Voltage, V
IH
Input Logic Low Voltage, V
IL
Input Logic High Current, I
IH
Input Logic Low Current, I
IL
Input Capacitance, C
IN
DIGITAL OUTPUTS (D0-D11)
Output Logic Sink Current, I
OL
Output Logic Source Current, I
OH
Output Capacitance, C
OUT
TIMING CHARACTERISTICS
Aperture Delay, t
AP
Aperture Jitter, t
AJ
Data Output Delay, t
OD
Data Output Hold, t
H
Data Latency, t
LAT
Clock Pulse Width (Low)
Clock Pulse Width (High)
POWER SUPPLY CHARACTERISTICS
Total Supply Current, I
CC
Analog Supply Current, AI
CC
Digital Supply Current, DI
CC1
Output Supply Current, DI
CC2
Power Dissipation
Offset Error PSRR,
∆V
OS
Gain Error PSRR,
∆FSE
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock off (clock low, hold mode).
V
IN
+ - V
IN
- = 2V
V
IN
+ - V
IN
- = 2V
V
IN
+ - V
IN
- = 2V
V
IN
+ - V
IN
- = 2V
V
IN
+ - V
IN
- = 2V
AV
CC
or DV
CC
= 5V
±5%
AV
CC
or DV
CC
= 5V
±5%
-
-
-
-
-
-
-
60
46
13
1
300
2
30
70
-
-
-
350
-
-
mA
mA
mA
mA
mW
LSB
LSB
For a Valid Sample (Note 2)
5MSPS Clock
5MSPS Clock
-
-
-
-
-
90
90
5
5
8
8
-
100
100
-
-
-
-
3
110
110
ns
ps (RMS)
ns
ns
Cycles
ns
ns
V
O
= 0.4V (Note 2)
DV
CC3
= 3.0V, V
O
= 0.4V
V
O
= 2.4V (Note 2)
DV
CC3
= 3.0V, V
O
= 2.4V
1.6
-
-0.2
-
-
-
1.6
-
-0.2
5
-
-
-
-
-
mA
mA
mA
mA
pF
V
CLK
= 5V
V
CLK
= 0V
2.0
-
-
-
-
-
-
-
-
7
-
0.8
10.0
10.0
-
V
V
µA
µA
pF
-
-
2.3
-
-
1
V
mA
-
-
-
3.5
7.8
450
-
-
-
V
kΩ
µA
-
-
-
3.5
-
200
-
1
-
V
mA
ppm/
o
C
TEST CONDITION
Differential Mode (Note 2)
MIN
1
TYP
2.3
MAX
4
UNITS
V
4
HI5805
Timing Waveforms
ANALOG
INPUT
CLOCK
INPUT
S
N-1
H
N - 1
S
N
H
N
S
N + 1
H
N + 1
S
N + 2
H
N + 2
S
N + 3
H
N + 3
S
N+4
H
N + 4
S
N + 5
H
N + 5
S
N + 6
H
N + 6
INPUT
S/H
1ST
STAGE
B
1, N - 1
B
1, N
B
1, N + 1
B
1, N + 2
B
1, N + 3
B
1, N + 4
B
1, N + 5
2ND
STAGE
B
2, N - 2
B
2, N - 1
B
2, N
B
2, N + 1
B
2, N + 2
B
2, N + 3
B
2, N + 4
3RD
STAGE
4TH
STAGE
B
3, N - 2
B
3, N - 1
B
3, N
B
3, N + 1
B
3, N + 2
B
3, N + 3
B
3, N + 4
B
4, N - 3
B
4, N - 2
B
4, N - 1
B
4, N
B
4, N + 1
B
4, N + 2
B
4, N + 3
DATA
OUTPUT
D
N - 3
D
N - 2
t
LAT
D
N - 1
D
N
D
N + 1
D
N + 2
D
N + 3
NOTES:
4. S
N
: N-th sampling period.
5. H
N
: N-th holding period.
6. B
M , N
: M-th stage digital output corresponding to N-th sampled input.
7. D
N
: Final data output corresponding to N-th sampled input.
FIGURE 1. INTERNAL CIRCUIT TIMING
ANALOG
INPUT
t
AP
t
AJ
CLOCK
INPUT
1.5V
1.5V
t
OD
t
H
2.0V
DATA N - 1
0.8V
DATA N
DATA
OUTPUT
FIGURE 2. INPUT-TO-OUTPUT TIMING
5
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