8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs
with Sequencer in 20-Lead TSSOP
AD7908/AD7918/AD7928
FEATURES
Fast Throughput Rate: 1 MSPS
Specified for AV
DD
of 2.7 V to 5.25 V
Low Power:
6.0 mW Max at 1 MSPS with 3 V Supply
13.5 mW Max at 1 MSPS with 5 V Supply
8 (Single-Ended) Inputs with Sequencer
Wide Input Bandwidth:
AD7928, 70 dB Min SINAD at 50 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface SPI
®
/QSPI™/
MICROWIRE™/DSP Compatible
Shutdown Mode: 0.5 A Max
20-Lead TSSOP Package
FUNCTIONAL BLOCK DIAGRAM
AV
DD
REF
IN
V
IN
0
•
•
•
•
•
•
•
•
•
•
•
•
•
V
IN
7
T/H
8-/10-/12-BIT
SUCCESSIVE
APPROXIMATION
ADC
I/P
MUX
SCLK
DOUT
SEQUENCER
CONTROL LOGIC
DIN
CS
GENERAL DESCRIPTION
The AD7908/AD7918/AD7928 are, respectively, 8-bit, 10-bit,
and 12-bit, high speed, low power, 8-channel, successive
approximation ADCs. The parts operate from a single 2.7 V
to 5.25 V power supply and feature throughput rates up to
1 MSPS. The parts contain a low noise, wide bandwidth track-
and-hold amplifier that can handle input frequencies in excess
of 8 MHz.
The conversion process and data acquisition are controlled using
CS
and the serial clock signal, allowing the device to easily inter-
face with microprocessors or DSPs. The input signal is sampled
on the falling edge of
CS
and conversion is also initiated at this
point. There are no pipeline delays associated with the part.
The AD7908/AD7918/AD7928 use advanced design techniques to
achieve very low power dissipation at maximum throughput rates.
At maximum throughput rates, the AD7908/AD7918/AD7928
consume 2 mA maximum with 3 V supplies; with 5 V supplies, the
current consumption is 2.7 mA maximum.
Through the configuration of the Control Register, the analog
input range for the part can be selected as 0 V to REF
IN
or 0 V to
2 REF
IN
, with either straight binary or twos complement out-
put coding. The AD7908/AD7918/AD7928 each feature eight
single-ended analog inputs with a channel sequencer to allow a
preprogrammed selection of channels to be converted sequentially.
The conversion time for the AD7908/AD7918/AD7928 is deter-
mined by the SCLK frequency, which is also used as the master
clock to control the conversion.
AD7908/AD7918/AD7928
V
DRIVE
GND
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption.
The AD7908/AD7918/AD7928 offer up to 1 MSPS throughput
rates. At the maximum throughput rate with 3 V supplies, the
AD7908/AD7918/AD7928 dissipate just 6 mW of power
maximum.
2. Eight Single-Ended Inputs with a Channel Sequencer.
A sequence of channels can be selected, through which the
ADC will cycle and convert on.
3. Single-Supply Operation with V
DRIVE
Function.
The AD7908/AD7918/AD7928 operate from a single 2.7 V to
5.25 V supply. The V
DRIVE
function allows the serial interface
to connect directly to either 3 V or 5 V processor systems
independent of AV
DD
.
4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. The parts also feature various shutdown
modes to maximize power efficiency at lower throughput rates.
Current consumption is 0.5 µA max when in full shutdown.
5. No Pipeline Delay.
The parts feature a standard successive approximation ADC
with accurate control of the sampling instant via a
CS
input
and once off conversion control.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD7908/AD7918/AD7928
AD7908–SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)
2
Signal-to-Noise Ratio (SNR)
2
Total Harmonic Distortion (THD)
2
Peak Harmonic or Spurious Noise
(SFDR)
2
Intermodulation Distortion (IMD)
2
Second Order Terms
Third Order Terms
Aperture Delay
Aperture Jitter
Channel-to-Channel Isolation
2
Full Power Bandwidth
DC ACCURACY
2
Resolution
Integral Nonlinearity
Differential Nonlinearity
0 V to REF
IN
Input Range
Offset Error
Offset Error Match
Gain Error
Gain Error Match
0 V to 2 REF
IN
Input Range
Positive Gain Error
Positive Gain Error Match
Zero Code Error
Zero Code Error Match
Negative Gain Error
Negative Gain Error Match
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
REFERENCE INPUT
REF
IN
Input Voltage
DC Leakage Current
REF
IN
Input Impedance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN3
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
3
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
49
49
–66
–64
–90
–90
10
50
–85
8.2
1.6
(AV
DD
= V
DRIVE
= 2.7 V to 5.25 V, REF
IN
= 2.5 V, f
SCLK
= 20 MHz, T
A
= T
MIN
to T
MAX
, unless
otherwise noted.)
Unit
dB min
dB min
dB max
dB max
fa = 40.1 kHz, fb = 41.5 kHz
dB typ
dB typ
ns typ
ps typ
dB typ
MHz typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
V
V
µA max
pF typ
V
µA max
k typ
V
DRIVE
V
DRIVE
V min
V max
µA max
pF max
–REF
IN
to +REF
IN
Biased about REF
IN
with
Twos Complement Output Coding
Test Conditions/Comments
f
IN
= 50 kHz Sine Wave, f
SCLK
= 20 MHz
B Version
1
f
IN
= 400 kHz
@ 3 dB
@ 0.1 dB
8
±0.2
±0.2
±0.5
±0.05
±0.2
±0.05
±0.2
±0.05
±0.5
±0.1
±0.2
±0.05
0 to REF
IN
0 to 2 REF
IN
±1
20
2.5
±1
36
0.7
0.3
±1
10
Guaranteed No Missed Codes to 8 Bits
Straight Binary Output Coding
RANGE Bit Set to 1
RANGE Bit Set to 0, AV
DD
/V
DRIVE
= 4.75 V to 5.25 V
±1% Specified Performance
f
SAMPLE
= 1 MSPS
Typically 10 nA, V
IN
= 0 V or V
DRIVE
V
DRIVE
– 0.2
V min
0.4
V max
±1
µA max
10
pF max
Straight (Natural) Binary
Twos Complement
800
300
300
1
ns max
ns max
ns max
MSPS max
–2–
I
SOURCE
= 200 µA, AV
DD
= 2.7 V to 5.25 V
I
SINK
= 200 µA
Coding Bit Set to 1
Coding Bit Set to 0
16 SCLK Cycles with SCLK at 20 MHz
Sine Wave Input
Full-Scale Step Input
See Serial Interface Section
REV. A
AD7908/AD7918/AD7928
AD7918–SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)
2
Signal-to-Noise Ratio (SNR)
2
Total Harmonic Distortion (THD)
2
Peak Harmonic or Spurious Noise
(SFDR)
2
Intermodulation Distortion (IMD)
2
Second Order Terms
Third Order Terms
Aperture Delay
Aperture Jitter
Channel-to-Channel Isolation
2
Full Power Bandwidth
DC ACCURACY
2
Resolution
Integral Nonlinearity
Differential Nonlinearity
0 V to REF
IN
Input Range
Offset Error
Offset Error Match
Gain Error
Gain Error Match
0 V to 2 REF
IN
Input Range
Positive Gain Error
Positive Gain Error Match
Zero Code Error
Zero Code Error Match
Negative Gain Error
Negative Gain Error Match
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
REFERENCE INPUT
REF
IN
Input Voltage
DC Leakage Current
REF
IN
Input Impedance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN3
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
3
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
(AV
DD
= V
DRIVE
= 2.7 V to 5.25 V, REF
IN
= 2.5 V, f
SCLK
= 20 MHz, T
A
= T
MIN
to T
MAX
, unless
otherwise noted.)
Unit
dB min
dB min
dB max
dB max
fa = 40.1 kHz, fb = 41.5 kHz
dB typ
dB typ
ns typ
ps typ
dB typ
MHz typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
V
V
µA max
pF typ
V
µA max
k typ
V
DRIVE
V
DRIVE
V min
V max
µA max
pF max
–REF
IN
to +REF
IN
Biased about REF
IN
with
Twos Complement Output Coding
Test Conditions/Comments
f
IN
= 50 kHz Sine Wave, f
SCLK
= 20 MHz
B Version
1
61
61
–72
–74
–90
–90
10
50
–85
8.2
1.6
10
±0.5
±0.5
±2
±0.2
±0.5
±0.2
±0.5
±0.2
±2
±0.2
±0.5
±0.2
0 to REF
IN
0 to 2 REF
IN
±1
20
2.5
±1
36
0.7
0.3
±1
10
f
IN
= 400 kHz
@ 3 dB
@ 0.1 dB
Guaranteed No Missed Codes to 10 Bits
Straight Binary Output Coding
RANGE Bit Set to 1
RANGE Bit Set to 0, AV
DD
/V
DRIVE
= 4.75 V to 5.25 V
±1% Specified Performance
f
SAMPLE
= 1 MSPS
Typically 10 nA, V
IN
= 0 V or V
DRIVE
V
DRIVE
– 0.2
V min
0.4
V max
±1
µA max
10
pF max
Straight (Natural) Binary
Twos Complement
800
300
300
1
–4–
ns max
ns max
ns max
MSPS max
I
SOURCE
= 200 µA, AV
DD
= 2.7 V to 5.25 V
I
SINK
= 200 µA
Coding Bit Set to 1
Coding Bit Set to 0
16 SCLK Cycles with SCLK at 20 MHz
Sine Wave Input
Full-Scale Step Input
See Serial Interface Section
REV. A
Embedded System
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