ispXPLD
®
5000MX Device Datasheet
June 2010
Select Devices Discontinued!
Product Change Notifications (PCNs) #09-10 has been issued to discontinue select
devices in this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
Ordering Part Number
LC5256MV-4F256C
LC5256MV-4FN256C
LC5256MV-5F256C
LC5256MV-5FN256C
LC5256MV-75F256C
LC5256MV-75FN256C
LC5256MV-5F256I
LC5256MV-5FN256I
LC5256MV-75F256I
LC5256MV-75FN256I
LC5256MB-4F256C
LC5256MB-4FN256C
LC5256MB-5F256C
LC5256MB-5FN256C
LC5256MB-75F256C
LC5256MB-75FN256C
LC5256MB-5F256I
LC5256MB-5FN256I
LC5256MB-75F256I
LC5256MB-75FN256I
LC5256MC-4F256C
LC5256MC-4FN256C
LC5256MC-5F256C
LC5256MC-5FN256C
LC5256MC-75F256C
LC5256MC-75FN256C
LC5256MC-5F256I
LC5256MC-5FN256I
LC5256MC-75F256I
LC5256MC-75FN256I
Product Status
Reference PCN
LC5256MV
Active / Orderable
LC5256MB
Active / Orderable
LC5256MC
Discontinued
PCN#09-10
5555 N.E. Moore Ct.
Hillsboro, Oregon 97124-6421 Phone (503) 268-8000
Internet: http://www.latticesemi.com
FAX (503) 268-8347
ispXPLD 5000MX Family
3.3V, 2.5V and 1.8V In-System Programmable
eXpanded Programmable Logic Device XPLD™ Family
February 2010
Data Sheet
TM
Features
Flexible Multi-Function Block (MFB)
Architecture
•
•
•
•
•
SuperWIDE™ logic (up to 136 inputs)
Arithmetic capability
Single- or Dual-port SRAM
FIFO
Ternary CAM
Expanded In-System Programmability (ispXP™)
• Instant-on capability
• Single chip convenience
• In-System Programmable via IEEE 1532
Interface
• Infinitely reconfigurable via IEEE 1532 or sys-
CONFIG™ microprocessor interface
• Design security
• 4.0ns pin-to-pin delays, 300MHz f
MAX
• Deterministic timing
SE
LE
D
IS C
C T
O D
N E
TI VI
N C
U E
ED S
sysCLOCK™ PLL Timing Control
High Speed Operation
• Multiply and divide between 1 and 32
• Clock shifting capability
• External feedback capability
Low Power Consumption
sysIO™ Interfaces
• LVCMOS 1.8, 2.5, 3.3V
– Programmable impedance
– Hot-socketing
– Flexible bus-maintenance (Pull-up, pull-
down, bus-keeper, or none)
– Open drain operation
• SSTL 2, 3 (I & II)
• HSTL (I, III, IV)
• PCI 3.3
• GTL+
• LVDS
• LVPECL
• LVTTL
• Typical static power: 20 to 50mA (1.8V),
30 to 60mA (2.5/3.3V)
• 1.8V core for low dynamic power
Easy System Integration
• 3.3V (5000MV), 2.5V (5000MB) and 1.8V
(5000MC) power supply operation
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL
interfaces
• IEEE 1149.1 interface for boundary scan testing
• sysIO quick configuration
• Density migration
• Multiple density and package options
• PQFP and fine pitch BGA packaging
• Lead-free package options
Table 1. ispXPLD 5000MX Family Selection Guide
Macrocells
256
8
ispXPLD 5256MX
ispXPLD 5512MX
512
16
ispXPLD 5768MX ispXPLD 51024MX
768
24
1,024
32
512K
2
Multi-Function Blocks
Maximum RAM Bits
sysCLOCK PLLs
Maximum CAM Bits
128K
48K
2
256K
96K
2
384K
2
144K
192K
t
PD
(Propagation Delay)
4.0ns
2.8ns
75K
141
4.5ns
5.0ns
5.2ns
t
S
(Register Set-up Time)
2.2ns
2.8ns
2.8ns
3.0ns
t
CO
(Register Clock to Out Time)
3.0ns
150K
3.2ns
225K
3.7ns
300K
f
MAX
(Maximum Operating Frequency)
300MHz
275MHz
250MHz
193/317
250MHz
317/381
Functional Gates
I/Os
149/193/253
208 PQFP
256 fpBGA
484 fpBGA
Packages
256 fpBGA
256 fpBGA
484 fpBGA
484 fpBGA
672 fpBGA
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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