®
ISL6548
Data Sheet
January 3, 2006
FN9188.2
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6548 provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller to
supply V
DDQ
during S0/S1 and S3 states. During S0/S1
state, a fully integrated sink-source regulator generates an
accurate (V
DDQ
/2) high current V
TT
voltage without the
need for a negative supply. Two LDO controllers are also
integrated for the GMCH core voltage regulation and for the
GMCH/CPU V
TT
termination voltage regulation.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. The switching
regulator provides a maximum static regulation tolerance of
±
2% over line, load, and temperature ranges. The output is
user-adjustable by means of external resistors down to 0.8V.
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the VIDPGD signal
indicates that the GMCH/CPU V
TT
termination voltage is
within spec and operational.
Each output is monitored for undervoltage events. The
switching regulator also has overvoltage and overcurrent
protection. Thermal shutdown is integrated.
Features
• Generates 4 Regulated Voltages
- Synchronous Buck PWM Controller for DDR V
DDQ
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference for DDR V
TT
- LDO Regulator for GMCH Core
- Sink/Source LDO Regulator for CPU/GMCH V
TT
Termination
• ACPI Compliant Sleep State Control
• Glitch-free Transitions During State Changes
• PWM Controller Drives Low Cost N-Channel MOSFETs
• 250kHz Constant Frequency Operation
• Tight Output Voltage Regulation
- All Outputs:
±
2% Over Temperature
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Under and Overvoltage Monitoring on All Outputs
• OCP on the Switching Regulator
• Integrated Thermal Shutdown Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Single and Dual Channel DDR Memory Power Systems in
ACPI compliant PCs
• Graphics Cards - GPU and Memory Supplies
• ASIC Power Supplies
• Embedded Processor and I/O Supplies
• DSP Supplies
Pinout
ISL6548 (6x6 QFN)
TOP VIEW
OCSET
22
21 DRIVE4
20 REFADJ4
19 DRIVE3
GND
29
18 FB3
17 FB4
16 COMP
15 FB
8
VDDQ
9
DDR_VTTSNS
10
DRIVE2_U
11
FB2
12
VIDPGD
13
DRIVE2_L
14
VREF_IN
PHASE
24
UGATE
LGATE
BOOT
GND
S5#
23
28
5VSBY
S3#
P12V
GND
DDR_VTT
DDR_VTT
VDDQ
1
2
3
4
5
6
7
27
26
25
Ordering Information
PART
PART NUMBER MARKING
ISL6548CRZA
(Note)
ISL6548CRZ
TEMP.
RANGE
(°C)
0 to 70
0 to 70
PACKAGE
PKG.
DWG. #
28 Ld 6x6 QFN L28.6x6
(Pb-free)
28 Ld 6x6 QFN L28.6x6
Tape and Reel
(Pb-free)
ISL6548CRZA-T ISL6548CRZ
(Note)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6548
Absolute Maximum Ratings
5VSBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V
P12V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14V
Absolute Boot Voltage, V
BOOT
. . . . . . . . . . . . . . . . . . . . . . . +15.0V
Upper Driver Supply Voltage, V
BOOT
- V
PHASE
. . . . . . . . . . . +6.0V
All other Pins . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance
θ
JA
(°C/W)
θ
JC
(°C/W)
QFN Package (Notes 1, 2) . . . . . . . . .
32
4
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
Recommended Operating Conditions
Supply Voltage on 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Supply Voltage on P12V . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2.
For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
5VSBY SUPPLY CURRENT
Nominal Supply Current
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
CC_S0
I
CC_S5
S3# & S5# HIGH, UGATE/LGATE Open
S5# LOW, S3# Don’t Care, UGATE/LGATE Open
5.50
-
7.00
700
8.00
850
mA
µA
POWER-ON RESET
Rising 5VSBY POR Threshold
Falling 5VSBY POR Threshold
Rising P12V POR Threshold
Falling P12V POR Threshold
OSCILLATOR AND SOFT-START
PWM Frequency
Ramp Amplitude
Soft-Start Interval
REFERENCE VOLTAGE
Reference Voltage
System Accuracy
V
DDQ
PWM CONTROLLER ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
Slew Rate
CONTROL I/O (S3# and S5#)
Low Level Input Threshold
High Level Input Threshold
0.75
-
-
-
-
2.2
V
V
GBWP
SR
Guaranteed By Design
-
15
-
80
-
6
-
-
-
dB
MHz
V/µs
V
REF
-
-2.0
0.800
-
-
+2.0
V
%
f
OSC
∆V
OSC
t
SS
220
-
6.5
250
1.5
8.2
280
-
9.5
kHz
V
ms
4.10
3.60
10.0
8.80
-
-
-
-
4.45
3.95
10.5
9.75
V
V
V
V
4
FN9188.2
January 3, 2006
ISL6548
Electrical Specifications
PARAMETER
PWM CONTROLLER GATE DRIVERS
UGATE and LGATE Source
UGATE and LGATE Sink
VTT REGULATOR
Upper Divider Impedance
Lower Divider Impedance
Maximum V
TT
Load Current
R
U
R
L
I
VTT_MAX
Periodic load applied with 30% duty cycle and
10ms period using ISL6548_6506EVAL1
evaluation board (see Application Note AN1123)
-
-
-3
2.5
2.5
-
-
-
3
kΩ
kΩ
A
I
GATE
I
GATE
-
-
-0.8
0.8
-
-
A
A
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics
(Continued)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
LINEAR REGULATORS
DC GAIN
Gain Bandwidth Product
Slew Rate
DRIVEn High Output Voltage
DRIVEn Low Output Voltage
DRIVEn High Output Source Current
DRIVEn Low Output Sink Current
VIDPGD
V
TT_GMCH/CPU
Rising Threshold
V
TT_GMCH/CPU
Falling Threshold
PROTECTION
OCSET Current Source
V
TT_DDR
Current Limit
V
DDQ
OV Level
V
DDQ
UV Level
V
TT_DDR
OV Level
V
TT_DDR
UV Level
V
GMCH
UV Level
V
TT_GMCH/CPU
UV Level
Thermal Shutdown Limit
V
FB
/V
REF
V
FB
/V
REF
V
TT
/V
VREF_IN
V
TT
/V
VREF_IN
V
FB4
/V
REF
V
FB2
/V
REF
T
SD
I
OCSET
By Design
S0/S3
S0/S3
S0
S0
S0
S0
By Design
18
-3.3
-
-
-
-
-
-
-
20
-
115
85
115
85
85
85
140
22
3.3
-
-
-
-
-
-
-
µA
A
%
%
%
%
%
%
°C
S0
S0
0.725
-
0.74
0.70
-
0.715
V
V
V
FB
= 770mV; V
DRIVEn
= 0V
V
FB
= 830mV; V
DRIVEn
= 10V
GBWP
SR
DRIVEn unloaded
Guaranteed By Design
-
15
-
9.75
-
-
-
80
-
6
10.0
0.16
1.7
1.2
-
-
-
-
0.50
-
-
dB
MHz
V/µs
V
V
mA
mA
5
FN9188.2
January 3, 2006
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