8T49N205NLGI datasheet, PDF - EEWORLD Datasheet

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8T49N205NLGI: DescriptionClock Synthesizer / Jitter Cleaner; Categorysemiconductor Analog mixed-signal IC; File Size725KB，41 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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8T49N205NLGI Overview

Clock Synthesizer / Jitter Cleaner

8T49N205NLGI Parametric

Parameter Name	Attribute value
Product Category	Clock Synthesizer / Jitter Cleaner
Manufacturer	IDT (Integrated Device Technology, Inc.)

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FemtoClock

NG Universal Frequency

Translator with Phase Build-Out

IDT8T49N205I

DATA SHEET

General Description

The IDT8T49N205I is a highly flexible FemtoClock® NG general

purpose, low phase noise Frequency Translator / Synthesizer with

Phase Build-Out (PBO) suitable for networking and communications

applications. It is able to generate any output frequency in the

0.98MHz - 312.5MHz range and most output frequencies in the

312.5MHz - 1,300MHz range (see Table 3 for details). A wide range

of input reference clocks and a range of low-cost fundamental mode

crystal frequencies may be used as the source for the output

frequency.

The IDT8T49N205I has three operating modes to support a very

broad spectrum of applications:

Frequency Synthesizer

Features

•

Fourth Generation FemtoClock® NG technology

Universal Frequency Translator/Frequency Synthesizer

•

Zero ppm frequency translation

Both outputs may be set to use 2.5V or 3.3V output levels

Programmable output frequency: 0.98MHz up to 1,300MHz

Two outputs, individually programmable as LVPECL or LVDS

Two differential inputs support the following input types:

LVPECL, LVDS, LVHSTL, HCSL

Input frequency range: 8kHz - 710MHz

Phase Build-Out minimizes output phase change on switchover

Crystal input frequency range: 16MHz - 40MHz

Two factory-set register configurations for power-up default state

•

Synthesizes output frequencies from a 16MHz - 40MHz

fundamental mode crystal.

Fractional feedback division is used, so there are no

requirements for any specific crystal frequency to produce the

desired output frequency with a high degree of accuracy.

Applications: PCI Express, Computing, General Purpose

Translates any input clock in the 16MHz - 710MHz frequency

range into any supported output frequency.

This mode has a high PLL loop bandwidth in order to track input

reference changes, such as Spread-Spectrum Clock

modulation, so it will not attenuate much jitter on the input

reference.

Applications: Networking & Communications.

Translates any input clock in the 8kHz -710MHz frequency

range into any supported output frequency.

This mode supports PLL loop bandwidths in the 10Hz - 580Hz

range and makes use of an external crystal to provide

significant jitter attenuation.

2) High-Bandwidth Frequency Translator

•

Power-up default configuration pin or register selectable

Configurations customized via One-Time Programmable ROM

Settings may be overwritten after power-up via I

C Serial interface for register programming

RMS phase jitter at 155.52MHz, using a 40MHz crystal

(12kHz - 20MHz): 378fs (typical), Low Bandwidth Mode (FracN)

Output supply voltage modes:

CCA

CCO

3.3V/3.3V/3.3V

3.3V/3.3V/2.5V

2.5V/2.5V/2.5V

-40°C to 85°C ambient operating temperature

3) Low-Bandwidth Frequency Translator

•

Pin Assignment

LOCK_IND

CCO

OE0

OE1

nQ0

nQ1

S_A0

S_A1

CONFIG

SCLK

SDATA

PLL_BYPASS

This device provides two factory-programmed default power-up

configurations burned into One-Time Programmable (OTP) memory.

The configuration to be used is selected by the CONFIG pin. The two

configurations are specified by the customer and are programmed by

IDT during the final test phase from an on-hand stock of blank

devices. The two configurations may be completely independent of

one another.

One usage example might be to install the device on a line card with

two optional daughter cards: an OC-12 option requiring a 622.08MHz

LVDS clock translated from a 19.44MHz input and a Gigabit Ethernet

option requiring a 125MHz LVPECL clock translated from the same

19.44MHz input reference.

To implement other configurations, these power-up default settings

can be overwritten after power-up using the I

C interface and the

device can be completely reconfigured. However, these settings

would have to be re-written next time the device powers-up.

CLK_ACTIVE

LF0

LF1

CCA

HOLDOVER

CLK0BAD

CLK1BAD

XTALBAD

30 29 28 27 26 25 24 23 22 21

IDT8T49N205I

40 Lead VFQFN

6mm x 6mm x 0.925mm

EPad 4.65mm x 4.65mm

NL Package

XTAL_IN

2 3 4

CLK_SEL

XTAL_OUT

5 6

CLK0

nCLK0

9 10

CLK1

Top View

IDT8T49N205ANLGI REVISION B JULY 9, 2013

nCLK1

8T49N205NLGI Related Products

	8T49N205NLGI	8T49N205NLGI8	8T49N205A-999NLGI8	8T49N205-003NLGI8
Description	Clock Synthesizer / Jitter Cleaner		Clock Synthesizer / Jitter Cleaner FemtoClock NG UFT Phase Build-Out	Clock Synthesizer / Jitter Cleaner Femto NG Clock Generator
Product Category	Clock Synthesizer / Jitter Cleaner	Clock Synthesizer / Jitter Cleaner	Clock Synthesizer / Jitter Cleaner	Clock Synthesizer / Jitter Cleaner
Manufacturer	IDT (Integrated Device Technology, Inc.)	IDT (Integrated Device Technology, Inc.)	IDT (Integrated Device Technology, Inc.)	IDT (Integrated Device Technology, Inc.)

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