BUK9Y104-100B
N-channel TrenchMOS logic level FET
Rev. 04 — 7 April 2010
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
Q101 compliant
Suitable for logic level gate drive
sources
Suitable for thermally demanding
environments due to 175 °C rating
1.3 Applications
12 V, 24 V and 42 V loads
Automotive systems
DC-to-DC converters
General purpose power switching
Solenoid drivers
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
Quick reference data
Parameter
drain-source
voltage
drain current
total power
dissipation
drain-source
on-state
resistance
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
V
GS
= 5 V; T
mb
= 25 °C;
see
Figure 1;
see
Figure 3
T
mb
= 25 °C
Min
-
-
-
Typ
-
-
-
Max Unit
100
V
14.8 A
59
W
Static characteristics
R
DSon
V
GS
= 10 V; I
D
= 5 A; T
j
= 25 °C
V
GS
= 5 V; I
D
= 5 A; T
j
= 25 °C;
see
Figure 11;
see
Figure 12
-
-
86
91
99
104
mΩ
mΩ
Avalanche ruggedness
E
DS(AL)S
non-repetitive
I
D
= 14.8 A; V
sup
≤
100 V;
drain-source
R
GS
= 50
Ω;
V
GS
= 5 V;
avalanche energy T
j(init)
= 25 °C; unclamped
gate-drain charge V
GS
= 5 V; I
D
= 5 A;
V
DS
= 80 V; see
Figure 13
-
-
35
mJ
Dynamic characteristics
Q
GD
-
4.7
-
nC
Nexperia
BUK9Y104-100B
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
4
mb
Pinning information
Symbol Description
S
S
S
G
D
source
source
source
gate
mounting base; connected to
drain
mbb076
Simplified outline
mb
Graphic symbol
D
G
S
1 2 3 4
SOT669 (LFPAK)
3. Ordering information
Table 3.
Ordering information
Package
Name
BUK9Y104-100B
LFPAK
Description
Version
plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669
Type number
BUK9Y104-100B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 04 — 7 April 2010
2 of 14
Nexperia
BUK9Y104-100B
N-channel TrenchMOS logic level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
T
mb
= 25 °C; V
GS
= 5 V; see
Figure 1;
see
Figure 3
T
mb
= 100 °C; V
GS
= 5 V; see
Figure 1
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive
drain-source
avalanche energy
repetitive drain-source
avalanche energy
T
mb
= 25 °C
t
p
≤
10 ms; pulsed; T
mb
= 25 °C
I
D
= 14.8 A; V
sup
≤
100 V; R
GS
= 50
Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped
see
Figure 2
[1][2][3]
[4]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
R
GS
= 20 kΩ
Min
-
-
-15
-
-
-
-
-55
-55
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
-
Max
100
100
15
14.8
10.48
59
59
175
175
14.8
59
35
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
T
mb
= 25 °C; t
p
≤
10 µs; pulsed;
see
Figure 3
T
mb
= 25 °C
Source-drain diode
Avalanche ruggedness
E
DS(AL)R
-
-
-
J
[1]
[2]
[3]
[4]
Maximum value not quoted. Repetitive rating defined in avalanche rating figure.
Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
Repetitive avalanche rating limited by an average junction temperature of 170 °C.
Refer to application note AN10273 for further information.
BUK9Y104-100B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 04 — 7 April 2010
3 of 14
Nexperia
BUK9Y104-100B
N-channel TrenchMOS logic level FET
20
I
D
(A)
15
003aac524
10
2
I
AL
(A)
10
003aac503
(1)
10
1
(2)
5
10
-1
(3)
0
0
50
100
150
T
mb
(°C)
200
10
-2
10
-3
10
-2
10
-1
1
t
AL
(ms)
10
Fig 1.
Continuous drain current as a function of
mounting base temperature
Fig 2.
Single-pulse and repetitive avalanche rating;
avalanche current as a function of avalanche
time
003aac624
10
2
Limit R
DSon
= V
DS
/ I
D
I
D
(A)
10µ s
10
100µ s
DC
1
1ms
10ms
100ms
10
-1
1
10
10
2
V
DS
(V)
10
3
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
BUK9Y104-100B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 04 — 7 April 2010
4 of 14
Nexperia
BUK9Y104-100B
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
Conditions
see
Figure 4
Min
-
Typ
-
Max
2.53
Unit
K/W
10
Z
th (j-mb)
(K/W)
δ
= 0.5
1
0.2
0.1
003aac483
10
-1
0.05
0.02
single shot
P
δ
=
t
p
T
t
p
T
t
10
-2
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration.
BUK9Y104-100B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 04 — 7 April 2010
5 of 14
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