DS2151QBX2 datasheet, PDF - EEWORLD Datasheet

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DS2151QBX2: DescriptionTelecom Interface ICs; CategoryWireless rf/communication Telecom circuit; File Size805KB，60 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS2151QBX2 Overview

Telecom Interface ICs

DS2151QBX2 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Maxim
Parts packaging code	LCC
package instruction	0.652 INCH, PLASTIC, LCC-44
Contacts	44
Reach Compliance Code	not_compliant
ECCN code	EAR99
Carrier type	T-1(DS1)
JESD-30 code	S-PQCC-J44
JESD-609 code	e0
length	16.5862 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	44
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC44,.7SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	245
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.572 mm
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	FRAMER
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	16.5862 mm
Base Number Matches	1

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DS2151Q

T1 Single-Chip Transceiver

www.maxim-ic.com

FEATURES

Complete DS1/ISDN-PRI Transceiver

Functionality

Line Interface Can Handle Both Long- and

Short-Haul Trunks

32-Bit or 128-Bit Jitter Attenuator

Generates DSX-1 and CSU Line Build-Outs

Frames to D4, ESF, and SLC-96

Formats

Dual On-Board Two-Frame Elastic Store Slip

Buffers that Connect to Backplanes Up to

8.192MHz

8-Bit Parallel Control Port That can be Used

on Either Multiplexed or Nonmultiplexed

Buses

Extracts and Inserts Robbed-Bit Signaling

Detects and Generates Yellow and Blue

Alarms

Programmable Output Clocks for Fractional

Fully Independent Transmit and Receive

Functionality

On-Board FDL Support Circuitry

Generates and Detects CSU Loop Codes

Contains ANSI One’s Density Monitor and

Enforcer

Large Path and Line Error Counters Including

BPV, CV, CRC6, and Framing Bit Errors

Pin Compatible with DS2153Q E1 Single-

Chip Transceiver

5V Supply; Low-Power CMOS

PIN CONFIGURATION

FUNCTIONAL BLOCKS

LONG & SHORT

HAUL LINE

INTERFACE

FRAMER

PARALLEL CONTROL

PORT

Dallas

DS2151Q

T1SCT

ACTUAL SIZE OF 44-PIN PLCC

TCHCLK

RD(DS)

AD7

AD6

AD5

AD4

AD3

AD2

AD1

ALE(AS)

(R/W)

RLINK

RLCLK

DVSS

RCLK

RCHCLK

RSER

RSYNC

RLOS/LOTC

SYSCLK

AD0

ELASTIC

STORES

DS2151Q

TSER

TCLK

DVDD

TSYNC

TLINK

TLCLK

TCHBLK

TRING

TVDD

TVSS

TTIP

RTIP

INT1

XTAL1

RCHBLK

RRING

ORDERING INFORMATION

PART

DS2151Q

DS2151Q+

DS2151QN

DS2151QN+

TEMP

RANGE

0°C to +70°C

-40°C to +85°C

PIN-

PACKAGE

44 PLCC

PLCC

Denotes lead-free/RoHS-compliant package.

Note:

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here:

www.maxim-ic.com/errata.

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XTAL2

ACLKI

RVDD

RVSS

INT2

BTS

REV: 011706

DS2151Q

LIST OF FIGURES

Figure 1-1. DS2151Q Block Diagram ......................................................................................................... 5

Figure 13-1. External Analog Connections............................................................................................... 43

Figure 13-2. Jitter Tolerance .................................................................................................................... 43

Figure 13-3. Transmit Waveform Template .............................................................................................. 44

Figure 13-4. Jitter Attenuation .................................................................................................................. 45

Figure 14-1. Receive Side D4 Timing....................................................................................................... 46

Figure 14-2. Receive Side ESF Timing .................................................................................................... 46

Figure 14-3. Receive Side Boundary Timing with Elastic Store(s) Disabled ............................................ 47

Figure 14-4. 1.544MHz Boundary Timing with Elastic Store(s) Enabled.................................................. 47

Figure 14-5. 2.048MHz Boundary Timing with Elastic Store(s) Enabled.................................................. 48

Figure 14-6. Transmit Side D4 Timing...................................................................................................... 48

Figure 14-7. Transmit Side ESF Timing ................................................................................................... 49

Figure 14-8. Transmit Side Boundary Timing with Elastic Store(s) Disabled ........................................... 50

Figure 14-9. Transmit Data Flow .............................................................................................................. 51

Figure 16-1. Intel Bus Read AC Timing.................................................................................................... 54

Figure 16-2. Intel Bus Write AC Timing .................................................................................................... 54

Figure 16-3. Motorola Bus AC Timing ...................................................................................................... 55

Figure 16-4. Receive Side AC Timing ...................................................................................................... 57

Figure 16-5. Transmit Side AC Timing ..................................................................................................... 59

LIST OF TABLES

Table 4-1. Output Pin Test Modes............................................................................................................ 13

Table 5-1. Receive T1 Level Indication .................................................................................................... 21

Table 5-2. Alarm Set and Clear Criteria ................................................................................................... 23

Table 6-1. Line Code Violation Counting Arrangements .......................................................................... 27

Table 6-2. Path Code Violation Counting Arrangements.......................................................................... 28

Table 6-3. Multiframes Out of Sync Counting Arrangements ................................................................... 29

Table 13-1. Source of RCLK Upon RCL................................................................................................... 40

Table 13-2. LBO Select in LICR ............................................................................................................... 41

Table 13-3. Transformer Specifications.................................................................................................... 41

Table 13-4. Crystal Selection Guidelines ................................................................................................. 42

Table 15-1. Recommended DC Characteristics ....................................................................................... 52

Table 15-2. Capacitance .......................................................................................................................... 52

Table 15-3. DC Characteristics ................................................................................................................ 52

Table 16-1. AC Characteristics—Parallel Port ......................................................................................... 53

Table 16-2. AC Characteristics—Receive Side ........................................................................................ 56

Table 16-3. AC Characteristics—Transmit Side ....................................................................................... 58

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DS2151Q

1 DETAILED DESCRIPTION

The DS2151Q T1 single-chip transceiver (SCT) contains all the necessary functions for connection to T1

lines whether they be DS-1 long haul or DSX-1 short haul. The clock recovery circuitry automatically

adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both DSX-1 line

build-outs as well as CSU build-outs of -7.5dB, -15dB, and -22.5dB. The on-board jitter attenuator

(selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The

framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also

used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set of 64

8-bit internal registers that the user can access to control the operation of the unit. Quick access via the

parallel control port allows a single micro to handle many T1 lines. The device fully meets all of the latest

T1 specifications including ANSI T1.403-199X, AT&T TR 62411 (12-90), and ITU G.703, G.704,

G.706, G.823, and I.431.

1.1 Introduction

The analog AMI waveform off of the T1 line is transformer coupled into the RRING and RTIP pins of

the DS2151Q. The device recovers clock and data from the analog signal and passes it through the jitter

attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing

pattern. If needed, the receive side elastic store can be enabled in order to absorb the phase and frequency

differences between the recovered T1 data stream and an asynchronous backplane clock which is

provided at the SYSCLK input.

The transmit side of the DS2151Q is totally independent from the receive side in both the clock

requirements and characteristics. Data can be either provided directly to the transmit formatter or via an

elastic store. The transmit formatter will provide the necessary data overhead for T1 transmission. Once

the data stream has been prepared for transmission, it is sent via the jitter attenuation mux to the

waveshaping and line driver functions. The DS2151Q will drive the T1 line from the TTIP and TRING

pins via a coupling transformer.

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DS2151QBX2 Related Products

	DS2151QBX2	DS2151QNB-W	DS2151QBX	DS2151QBX-TR	DS2151QB-	DS2151QB-TR	DS2151QNB-TR
Description	Telecom Interface ICs	Telecom Interface ICs	Telecom Interface ICs	Telecom Interface ICs	Telecom Interface ICs T1 Transceiver	Telecom Interface ICs	Telecom Interface ICs
Product Category	-	Telecom Interface ICs	-	Telecom Interface ICs	Telecom Interface ICs	Telecom Interface ICs	Telecom Interface ICs
Manufacturer	-	Maxim	-	Maxim	Maxim	Maxim	Maxim
Product	-	T1 Transceivers	-	T1 Transceivers	T1 Transceivers	T1 Transceivers	T1 Transceivers
Operating Supply Voltage	-	5 V	-	5 V	5 V	5 V	5 V
Maximum Operating Temperature	-	+ 85 C	-	+ 70 C	+ 70 C	+ 70 C	+ 85 C
Mounting Style	-	SMD/SMT	-	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT
Package / Case	-	PLCC-44	-	PLCC-44	PLCC-44	PLCC-44	PLCC-44
Data Rate	-	2.048 Mbps	-	2.048 Mbps	2.048 Mbps	2.048 Mbps	2.048 Mbps
Minimum Operating Temperature	-	- 40 C	-	0 C	0 C	0 C	- 40 C
Number of Channels	-	1 Channel	-	1 Channel	1 Channel	1 Channel	1 Channel
Supply Voltage - Max	-	5.25 V	-	5.25 V	5.25 V	5.25 V	5.25 V
Supply Voltage - Min	-	4.75 V	-	4.75 V	4.75 V	4.75 V	4.75 V
Unit Weight	-	0.084185 oz	-	0.084185 oz	0.084185 oz	0.084185 oz	0.084185 oz

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