LCD Segment Drivers
Multi-function LCD Segment Drivers
BU97530KVT
General Description
The BU97530KVT is 1/5, 1/4, 1/3 or 1/1 duty
general-purpose LCD driver that can be used for
frequency display in electronic tuners under the
control of a microcontroller. The BU97530KVT can
drive up to 445 LCD Segments directly. The
BU97530KVT can also control up to 9
general-purpose output ports.
These products also incorporate a key scan circuit
that accepts input from up to 30 keys to reduce
printed circuit board wring.
MAX 445 Segment(89segx5COM)
Key Specifications
Supply Voltage Range:
+2.7V to +6.0V
Operating Temperature Range:
-40°C to +85°C
Max Segments:
445 Segments
Display Duty:
1/1,1/3,1/4,1/5
selectable
Bias:
1/2, 1/3 selectable
Interface:
3wire serial interface
Packages
TQFP100V
W(Typ.)×D(Typ.)×H(Max.)
Features
Key input function for up to 30 keys (A key scan is
performed only when a key is pressed.)
Either 1/5, 1/4, 1/3 or 1/1 duty (static) can be
selected with the serial control data.
1/5 duty drive: Up to 445 segments can be driven
1/4 duty drive: Up to 360 segments can be driven
1/3 duty drive: Up to 270 segments can be driven
1/1 duty drive: Up to 90 segments can be driven
Serial data control of frame frequency for common
and segment output waveforms.
Serial data control of switching between the
segment output port , PWM output port and
general-purpose output port functions.(Max 9
ports)
Built-in OSC circuit
Integrated Power-on Reset circuit
No external component
Low power consumption design
Supports Line and Frame Inversion
TQFP100V
16.00mm x 16.00mm x 1.20mm
Applications
Car audio, Home electrical appliance,
Meter equipment etc.
Typical Application Circuit
Key Matrix
(P1/G1)
(P9/G9)
(General purpose/PWM ports)
(For use control of backlight)
KS1/S79
KI1/S85
|
KS6/S84
|
KI5/S89
+5V
(Note1)
VDD
COM1
COM2
COM3
COM4
COM5/S78
S1/P1/G1
LCD Panel
(Up to 445
S9/P9/G9
S10
Segments)
From
Control
To Control
SCE
SCL
SDI
SDO
S77
OSC/S90
(Note1) Insert capacitors between VDD and VSS C≥0.1uF
Figure 1. Typical Application Circuit
○Product
structure：Silicon monolithic integrated circuit
.
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© 2014 ROHM Co., Ltd. All rights reserved.
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○This
product is not designed protection against radioactive rays
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BU97530KVT
Absolute Maximum Ratings(Ta = 25°C, VSS = 0.0V)
Parameter
Maximum supply voltage
Input voltage
Allowable loss
Operating temperature
Storage temperature
Symbol
VDD max
VIN1
VIN2
Pd
Topr
Tstg
Conditions
VDD
SCE, SCL, SDI
KI1 to KI5
Ratings
-0.3 to +6.5
-0.3 to +6.5
-0.3 to +6.5
1.49
(Note2)
-40 to +85
-55 to +125
Datasheet
Unit
V
V
V
W
°C
°C
(Note2) Derate by 1.49mW/°C when operating above Ta=25°C (when mounted in ROHM’s standard board).
Caution:
Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over the
absolute maximum ratings.
Recommended Operating Conditions (Ta = -40 to +85°C, VSS = 0.0V)
Parameter
Supply Voltage
Symbol
VDD
Conditions
Min
2.7
Ratings
Typ
5.0
Max
6.0
Unit
V
Electrical Characteristics (Ta = -40 to +85°C, VDD = 2.7V to 6.0V, VSS = 0.0V)
Parameter
Hysteresis
Power-on Detection
Voltage
“H” Level Input Voltage
Symbol
VH1
VH2
VDET
VIH1
VIH2
VIH3
VIL1
VIF
RPD
IOFFH
IIH1
IIL1
VOH1
VOH2
VOH3
VOH4
VOL1
VOL2
VOL3
VOL4
VOL5
VMID1
VMID2
VMID3
VMID4
VMID5
VMID6
Current Consumption
IDD1
IDD2
Pin
SCE, SCL, SDI
KI1 to KI5
VDD
SCE, SCL, SDI
SCE, SCL, SDI
KI1 to KI5
SCE, SCL, SDI
KI1 to KI5
KI1 to KI5
KI1 to KI5
SDO
SCE, SCL, SDI
SCE, SCL, SDI
S1 to S90
COM1 to COM5
P1/G1 to P9/G9
KS1 to KS6
S1 to S90
COM1 to COM5
P1/G1 to P9/G9
KS1 to KS6
SDO
S1 to S90
COM1 to COM5
S1 to S90
S1 to S90
COM1 to COM5
COM1 to COM5
VDD
VDD
4.0V
≤
VDD
≤
6.0V
2.7V
≤
VDD < 4.0V
Conditions
Min
-
-
1.4
0.4VDD
0.8VDD
0.7VDD
0
VDD=5.0V
VO=6.0V
VI = 5.5V
VI = 0V
IO = -20µA,
VLCD=1.00*VDD
IO = -100µA,
VLCD=1.00*VDD
IO = -1mA
IO = -500uA
IO = 20µA
IO = 100µA
IO = 1mA
IO = 25uA
IO = 1mA
1/2 bias IO = ±20µA
VLCD=1.00*VDD
1/2 bias IO = ±100µA
VLCD=1.00*VDD
1/3 bias IO = ±20µA
VLCD=1.00*VDD
1/3 bias IO = ±20µA
VLCD=1.00*VDD
1/3 bias IO = ±100µA
VLCD=1.00*VDD
1/3 bias IO = ±100µA
VLCD=1.00*VDD
Power-saving mode
VDD = 5.0V
Output open, 1/2 bias
Frame frequency=80Hz
VLCD=1.00*VDD
VDD = 5.0V
Output open,1/3 bias
Frame frequency=80Hz
VLCD=1.00*VDD
-
50
-
-
-5.0
VDD-0.9
VDD-0.9
VDD-0.9
VDD-1.0
-
-
-
0.2
-
1/2VDD
-0.9
1/2VDD
-0.9
2/3VDD
-0.9
1/3VDD
-0.9
2/3VDD
-0.9
1/3VDD
-0.9
-
-
Limit
Typ
0.03VDD
0.1VDD
1.8
-
-
-
-
-
100
-
-
-
-
-
-
VDD-0.5
-
-
-
0.5
0.1
-
-
-
-
-
-
-
100
Max
-
-
2.2
VDD
VDD
VDD
0.2VDD
0.05VDD
250
6.0
5.0
-
-
-
-
VDD-0.2
0.9
0.9
0.9
1.5
0.5
1/2VDD
+0.9
1/2VDD
+0.9
2/3VDD
+0.9
1/3VDD
+0.9
2/3VDD
+0.9
1/3VDD
+0.9
15
200
µA
-
130
250
V
Unit
V
V
V
V
V
V
V
V
KΩ
µA
µA
µA
“L” Level Input Voltage
Input Floating Voltage
Pull-down Resistance
Output Off Leakage
Current
“H” Level Input Current
“L” Level Input Current
“H” Level
Output Voltage
“L” Level
Output Voltage
V
Middle Level
Output Voltage
V
IDD3
VDD
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BU97530KVT
Oscillation Characteristics (Ta = -40 to +85°C, VDD = 2.7V to 6.0V, VSS = 0.0V)
Parameter
Oscillator Frequency 1
Oscillator Frequency 2
External Clock
Frequency
(Note3)
External Clock Duty
Symbol
fosc1
fosc2
fosc3
tdty
Pin
-
-
OSC/S90
OSC/S90
Conditions
VDD = 2.7V to 6.0V
VDD = 5V
External clock mode
(OC=1)
External clock mode
(OC=1)
Min
300
510
30
30
Limit
Typ
-
600
-
50
Datasheet
Max
720
690
1000
70
Unit
kHz
kHz
kHz
%
(Note3) Frame frequency is decided external frequency and dividing ratio of FC0,FC1,FC2 setting.
【Reference
Data】
700
650
600
fosc[kHz]
550
VDD = 6.0V
VDD = 5.0V
VDD = 3.3V
500
450
400
350
300
-40
-20
0
20
40
60
80
Temperature[°C]
VDD = 2.7V
Figure 4. Typical Temperature Characteristics
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BU97530KVT
MPU Interface Characteristics (Ta = -40 to +85°C, VDD = 2.7V to 6.0V, VSS = 0.0V)
Parameter
Data Setup Time
Data Hold Time
SCE Wait Time
SCE Setup Time
SCE Hold Time
Clock Cycle Time
High-level Clock Pulse
Width
Low-level Clock Pulse
Width (Write)
Low-Level Clock Pulse
Width (Read)
Rise Time
Fall Time
SDO Output Delay
Time
SDO Rise Time
Symbol
tds
tdh
tcp
tcs
tch
tccyc
tchw
tclww
tclwr
tr
tf
tdc
tdr
Pin
SCL, SDI
SCL, SDI
SCE, SCL
SCE, SCL
SCE, SCL
SCL
SCL
SCL
SCL
SCE, SCL, SDI
SCE, SCL, SDI
SDO
SDO
RPU=4.7KΩ
CL=10pf
(Note4)
RPU=4.7KΩ
CL=10pf
(Note4)
RPU=4.7KΩ
CL=10pF
(Note4)
Conditions
Min
120
120
120
120
120
320
120
120
1.6
-
-
-
-
Limit
Typ
-
-
-
-
-
-
-
-
-
160
160
-
-
Datasheet
Max
-
-
-
-
-
-
-
-
-
-
-
1.5
1.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
µs
µs
(Note4) Since SDO is an open-drain output, “tdc” and “tdr” depend on the resistance of the pull-up resistor RPU and the load capacitance CL.
RPU: 1kΩ≤RPU≤10kΩ is recommended.
CL: A parasitic capacitance to VSS in an application circuit. Any component is not necessary to be attached.
Power supply for I/O level
R
PU
SDO
C
L
Host
1. When SCL is stopped at the low level
VIH1, VIH2
SCE
tccyc
tchw
VIH1, VIH2
VIL1
tclww
tclwr
SCL
VIL1
tr
tf
tcs
tch
SDI
VIH1, VIH2
VIL1
tds
tdh
VOL5
SDO
tdc
tdr
2. When SCL is stopped at the high level
SCE
tccyc
tclww
tchw
VIH1,VIH2
VIL1
VIH1, VIH2
VIL1
tclwr
SCL
tf
tr
tcp
tch
SDI
VIH1,VIH2
VIL1
tds
tdh
VOL5
SDO
tdc
tdr
Figure 5.Serial Interface Timing
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© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
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TSZ02201-0P4P0D300570-1-2
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