Si3230
P
RO
SLIC
®
P
R O GRA MM A B LE
CMOS SLIC
R
I N G I N G
/ B
A T T E R Y
V
O L TAG E
G
ENERATION
Features
Software programmable signal
Software Programmable SLIC with
codec interface
generation and audio processing:
DTMF generation and decoding
Software programmable internal
12 kHz/16 kHz pulse metering
balanced ringing up to 90 V
PK
generation
(5 REN up to 4 kft, 3 REN up to 8 kft)
Phase-continuous FSK (caller ID)
Integrated battery supply with dynamic
generation
voltage output
On-chip
WITH
Loop
closure and ring trip thresholds and
filtering
Applications
BCM11xx
Interface to Broadcom devices
residential gateway
BCM3341 VOIP processor
BCM33xx cable modem
Voice over IP
Terminal adapters
Fixed cellular terminal
Description
The Si3230 ProSLIC
®
is a low-voltage CMOS device that provides a multi-functional
subscriber line interface ideal for customer premise equipment (CPE) applications.
The ProSLIC integrates subscriber line interface circuit (SLIC) and battery generation
functionality into a single CMOS integrated circuit. The integrated battery supply
continuously adapts its output voltage to minimize power and enables the entire
solution to be powered from a single 3.3 V (Si3230M only) or 5 V supply. The ProSLIC
controls the phone line through Silicon Labs’ Si3201 Linefeed IC or discrete circuitry.
Si3230 features include software-configurable 5 REN internal ringing up to 90 V
PK
,
DTMF generation and decoding, and a comprehensive set of telephony signaling
capabilities for operation with only one hardware solution. The ProSLIC is packaged in
a 38-pin QFN or TSSOP, and the Si3201 is packaged in a thermally-enhanced 16-pin
SOIC.
NC
FSYNC
RESET
SDCH
SDCL
V
DDA1
IREF
CAPP
QGND
CAPM
STIPDC
SRINGDC
TEST2
PCLK
INT
CS
SCLK
SDI
SDO
29
28
27
26
25
24
23
22
21
SPI control interface
Extensive programmable interrupts
100% software configurable global
Ringing frequency, amplitude, cadence,
solution
and waveshape
2-wire ac impedance
Lead-Free and RoHS-compliant
constant current feed (20 to 41 mA)
package options available
Software programmable linefeed
parameters:
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dc-dc converter continuously
minimizes power in all operating modes
Entire solution can be powered from a
single 3.3 V or 5 V supply
3.3 V to 35 V dc input range
Dynamic 0 V to –94.5 V output
Dual
audio tone generators
Smooth and abrupt polarity reversal
Ordering Information
See page 103.
Extensive test and diagnostic
features
Realtime
GR-909
dc linefeed measurement
line test capabilities
Pin Assignments
QFN Package
1 38 37 36 35 34 33 32 31
30
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20
SDITHRU
DCDRV
DCFF
TEST1
GNDD
VDDD
ITIPN
ITIPP
V
DDA2
IRINGP
IRINGN
IGMP
Patents pending
U.S. Patent #6,567,521
U.S. Patent #6,812,744
Other patents pending
Functional Block Diagram
INT RESET
SPI Control Interface
CS
SCLK
SDO
SDI
Si3230
Ringing Generator
Loop Closure Detect
Ring Trip Detect Line
Diagnostics
SLIC
Linefeed Control
Linefeed
Interface
Tip
Ring
Tone Generators
FSK Caller ID
Pulse Metering
Impedance Synth
DTMF Decoder
PLL
FSYNC
PCLK
Linefeed Monitor
DC–DC Converter Controller
Battery
Preliminary Rev. 0.96 2/05
Copyright © 2005 by Silicon Laboratories
STIPE
SVBAT
SRINGE
STIPAC
SRINGAC
IGMN
GNDA
Si3230
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
2
Si3230
Preliminary Rev. 0.96
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Si3230
T
ABLE
Section
OF
C
ONTENTS
Page
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Preliminary Rev. 0.96
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1. Linefeed Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2. Battery Voltage Generation and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3. Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.5. Pulse Metering Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.6. DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.7. Two-Wire Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.8. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.9. Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.10. Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4. Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
4.1. DTMF Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
4.2. Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.3. Digital Programmable Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.4. SLIC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.5. FSK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
5. Pin Descriptions: Si3230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
6. Pin Descriptions: Si3201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7. Ordering Guide1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
8. Package Outline: 38-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
9. Package Outline: 38-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
10. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
3
Si3230
1. Electrical Specifications
Table 1. Absolute Maximum Ratings and Thermal Information
1
Parameter
DC Supply Voltage
Input Current, Digital Input Pins
Digital Input Voltage
ESD, Human Body Model
Operating Temperature Range
2
Storage Temperature Range
T
A
T
STG
JA
JA
P
D
Symbol
Si3230
V
DDD
, V
DDA1
, V
DDA2
I
IN
V
IND
–0.5 to 6.0
±10
–0.3 to (V
DDD
+ 0.3)
2000
–40 to 100
–40 to 150
70
35
V
mA
V
V
C
C
C/W
C/W
W
V
V
V
V
C
C
C/W
W
Value
Unit
TSSOP-38 Thermal Resistance, Typical
QFN-38 Thermal Resistance, Typical
Continuous Power Dissipation
2
DC Supply Voltage
Battery Supply Voltage
Input Voltage: TIP, RING, SRINGE, STIPE pins
Operating Temperature Range
2
Storage Temperature Range
Input Voltage: ITIPP, ITIPN, IRINGP, IRINGN pins
SOIC-16 Thermal Resistance, Typical
3
Continuous Power Dissipation
2
Notes:
1.
Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2.
Operation above 125
o
C junction temperature may degrade device reliability.
3.
Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad.
4
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0.7
Si3201
V
DD
–0.5 to 6.0
–104
V
BAT
V
IN
T
A
V
INHV
–0.3 to (V
DD
+ 0.3)
–40 to 100
–40 to 150
55
1.0
T
STG
JA
P
D
Preliminary Rev. 0.96
(V
BAT
– 0.3) to (V
DD
+ 0.3)
Si3230
Table 2. Recommended Operating Conditions
Parameter
Ambient Temperature
Ambient Temperature
Si3230 Supply Voltage
Si3201 Supply Voltage
Si3201 Battery Voltage
Symbol
T
A
T
A
V
DDD
,V
DDA1
,V
DDA2
V
DD
V
BAT
V
BATH
= V
BAT
Test Condition
K-grade
B-grade
Min*
0
–40
3.13
3.13
–96
Typ
25
25
3.3/5.0
3.3/5.0
—
Max*
70
85
5.25
5.0
0
Unit
o
C
o
C
V
V
V
Table 3. AC Characteristics
Parameter
Overload Level
(V
DDA
, V
DDD
= 3.13 to 5.25 V, T
A
= 0 to 70°C for K-Grade, –40 to 85°C for B-Grade)
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Test Condition
THD = 1.5%
Min
2.5
45
—
Typ
—
TX/RX Performance
0 dBm0, Active off-hook,
and OHT, any Zac
200 Hz to 3.4 kHz
—
—
30
—
35
—
Noise Performance
C-Message Weighted
3 kHz flat
Psophometric Weighted
—
—
—
—
RX and TX, DC to 3.4 kHz
40
—
RX and TX, DC to 3.4 kHz
40
—
RX and TX, DC to 3.4 kHz
40
—
Preliminary Rev. 0.96
*Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25
o
C unless otherwise stated.
Product specifications are only guaranteed when the typical application circuit (including component tolerances) is
used.
Max
—
—
Unit
V
PK
dB
dB
dB
dBrnC
dBmP
dBrn
dB
dB
dB
Audio Tone Generator
Signal-to-Distortion Ratio
1
Intermodulation Distortion
2-Wire Return Loss
–45
—
Idle Channel Noise
3
15
–75
18
—
—
—
PSRR from VDDA
PSRR from VBAT
PSRR from VDDD
Notes:
1.
Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
2.
The quantization errors inherent in the
/A-law
companding process can generate slightly worse gain tracking
performance in the signal range of 3 dB to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
3.
The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
4.
Assumes normal distribution of betas.
5
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