Data Sheet
FEATURES
High performance member of pin-compatible
TxDAC product family
Excellent spurious-free dynamic range performance
SFDR to Nyquist
83 dBc at 5 MHz output
80 dBc at 10 MHz output
73 dBc at 20 MHz output
SNR at 5 MHz output, 125 MSPS: 77 dB
Twos complement or straight binary data format
Differential current outputs: 2 mA to 20 mA
Power dissipation: 135 mW at 3.3 V
Power-down mode: 15 mW at 3.3 V
On-chip 1.2 V reference
CMOS-compatible digital interface
28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP packages
Edge-triggered latches
14-Bit, 210 MSPS TxDAC
®
D/A Converter
AD9744
APPLICATIONS
Wideband communication transmit channel
Direct IFs
Base stations
Wireless local loops
Digital radio links
Direct digital synthesis (DDS)
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
3.3V
REFLO
1.2V REF
REFIO
FS ADJ
R
SET
3.3V
DVDD
DCOM
CLOCK
CLOCK
SEGMENTED
SWITCHES
LSB
SWITCHES
LATCHES
150pF
AVDD
CURRENT
SOURCE
ARRAY
ACOM
0.1µF
AD9744
IOUTA
IOUTB
MODE
02913-001
DIGITAL DATA INPUTS (DB13–DB0)
SLEEP
Figure 1.
GENERAL DESCRIPTION
The
AD9744
1
is a 14-bit resolution, wideband, third generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC family,
consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is
specifically optimized for the transmit signal path of communi-
cation systems. All of the devices share the same interface options,
small outline package, and pinout, providing an upward or
downward component selection path based on performance,
resolution, and cost. The
AD9744
offers exceptional ac and dc
performance while supporting update rates up to 210 MSPS.
The
AD9744’s
low power dissipation makes it well suited for
portable and low power applications. Its power dissipation can
be further reduced to a mere 60 mW with a slight degradation
in performance by lowering the full-scale current output. Also,
a power-down mode reduces the standby power dissipation to
approximately 15 mW. A segmented current source architecture
is combined with a proprietary switching technique to reduce
spurious components and enhance dynamic performance.
Edge-triggered input latches and a 1.2 V temperature compensated
band gap reference have been integrated to provide a complete
monolithic DAC solution. The digital inputs support 3 V
CMOS logic families.
PRODUCT HIGHLIGHTS
1. The
AD9744
is the 14-bit member of the pin compatible TxDAC
family, which offers excellent INL and DNL performance.
2. Data input supports twos complement or straight binary data
coding.
3. High speed, single-ended CMOS clock input supports
210 MSPS conversion rate.
4. Low power: Complete CMOS DAC function operates on
135 mW from a 2.7 V to 3.6 V single supply. The DAC full-
scale current can be reduced for lower power operation, and a
sleep mode is provided for low power idle periods.
5. On-chip voltage reference: The
AD9744
includes a 1.2 V
temperature compensated band gap voltage reference.
6. Industry-standard 28-lead SOIC, 28-lead TSSOP, and 32-lead
LFCSP packages.
1
Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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AD9744
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
Dynamic Specifications ............................................................... 4
Digital Specifications ................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 12
Functional Description .................................................................. 13
Reference Operation .................................................................. 13
Data Sheet
Reference Control Amplifier .................................................... 13
DAC Transfer Function ............................................................. 14
Analog Outputs .......................................................................... 14
Digital Inputs .............................................................................. 15
Clock Input.................................................................................. 15
DAC Timing................................................................................ 16
Power Dissipation....................................................................... 16
Applying the AD9744 ................................................................ 17
Differential Coupling Using a Transformer............................ 17
Differential Coupling Using an Op Amp ................................ 17
Single-Ended Unbuffered Voltage Output .............................. 18
Single-Ended, Buffered Voltage Output Configuration ........ 18
Power and Grounding Considerations, Power Supply
Rejection ...................................................................................... 18
Evaluation Board ............................................................................ 20
General Description ................................................................... 20
Outline Dimensions ....................................................................... 30
Ordering Guide............................................................................... 31
5/03—Rev. 0 to Rev. A
Added 32-Lead LFCSP Package ....................................... Universal
Edits to Features.................................................................................1
Edits to Product Highlights..............................................................1
Edits to DC Specifications ................................................................2
Edits to Dynamic Specifications ......................................................3
Edits to Digital Specifications ..........................................................4
Edits to Absolute Maximum Ratings ..............................................5
Edits to Thermal Characteristics .....................................................5
Edits to Ordering Guide ...................................................................5
Edits to Pin Configuration ...............................................................6
Edits to Pin Function Descriptions .................................................6
Edits to Figure 2 .................................................................................7
Replaced TPCs 1, 4, 7, and 8 ............................................................8
Edits to Figure 3 .............................................................................. 10
Edits to Functional Description ................................................... 10
Added Clock Input Section ........................................................... 12
Added Figure 7 ............................................................................... 12
Edits to DAC Timing Section ....................................................... 12
Edits to Sleep Mode Operation Section....................................... 13
Edits to Power Dissipation Section .............................................. 13
Renumbered Figures 8 to Figure 26 ............................................. 13
Added Figure 11 ............................................................................. 13
Added Figure 27 to Figure 35 ....................................................... 21
Updated Outline Dimensions ....................................................... 26
REVISION HISTORY
12/13—Rev. B to Rev. C
Added Table 5; Renumbered Sequentially .................................... 6
Added Exposed Pad Note to Figure 4 and Table 6, Pin
Configurations and Function Descriptions Section .................... 7
Moved Terminology Section ......................................................... 12
Updated Outline Dimensions ....................................................... 30
Changes to Ordering Guide .......................................................... 31
4/05—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to General Description .................................................... 1
Changes to Product Highlights....................................................... 1
Changes to DC Specifications ......................................................... 3
Changes to Dynamic Specifications ............................................... 4
Changes to Pin Function Description ........................................... 7
Changes to Figure 6 and Figure 9 ................................................... 9
Inserted New Figure 10; Renumbered Sequentially .................... 9
Changes to Figure 12, Figure 13, Figure 14, and Figure 15 ...... 10
Changes to Figure 22 Caption ...................................................... 11
Inserted New Figure 23; Renumbered Sequentially .................. 11
Changes to Functional Description ............................................. 13
Changes to Reference Operation Section .................................... 13
Added Figure 25; Renumbered Sequentially .............................. 13
Changes to Digital Inputs Section ................................................ 15
Changes to Figure 31 and Figure 32............................................. 16
Updated Outline Dimensions ....................................................... 30
Changes to Ordering Guide .......................................................... 31
Rev. C | Page 2 of 32
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
OUTFS
= 20 mA, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DC ACCURACY
1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current
2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current
3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance (External Reference)
Small Signal Bandwidth
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD
DVDD
CLKVDD
Analog Supply Current (I
AVDD
)
Digital Supply Current (I
DVDD
)
4
Clock Supply Current (I
CLKVDD
)
Supply Current Sleep Mode (I
AVDD
)
Power Dissipation
4
Power Dissipation
5
Power Supply Rejection Ratio—AVDD
6
Power Supply Rejection Ratio—DVDD
6
OPERATING RANGE
1
2
AD9744
Min
14
−5
−3
−0.02
−0.5
−0.5
2
−1
Typ
Max
Unit
Bits
LSB
LSB
% of FSR
% of FSR
% of FSR
mA
V
kΩ
pF
V
nA
V
kΩ
MHz
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
±0.8
±0.5
+5
+3
+0.02
+0.5
+0.5
20
+1.25
±0.1
±0.1
100
5
1.14
1.20
100
1.26
0.1
7
0.5
0
±50
±100
±50
1.25
2.7
2.7
2.7
3.3
3.3
3.3
33
8
5
5
135
145
3.6
3.6
3.6
36
9
6
6
145
+1
+0.04
+85
−1
−0.04
−40
V
V
V
mA
mA
mA
mA
mW
mW
% of FSR/V
% of FSR/V
°C
Measured at IOUTA, driving a virtual ground.
Nominal full-scale current, I
OUTFS
, is 32 times the I
REF
current.
3
An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
4
Measured at f
CLOCK
= 25 MSPS and f
OUT
= 1 MHz.
5
Measured as unbuffered voltage output with I
OUTFS
= 20 mA and 50 Ω R
LOAD
at IOUTA and IOUTB, f
CLOCK
= 100 MSPS and f
OUT
= 40 MHz.
6
±5% power supply variation.
Rev. C | Page 3 of 32
AD9744
DYNAMIC SPECIFICATIONS
Data Sheet
T
MIN
to T
MAX
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
OUTFS
= 20 mA, differential transformer coupled output, 50 Ω doubly
terminated, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate (f
CLOCK
)
Output Settling Time (t
ST
) (to 0.1%)
1
Output Propagation Delay (t
PD
)
Glitch Impulse
Output Rise Time (10% to 90%)
1
Output Fall Time (10% to 90%)
1
Output Noise (I
OUTFS
= 20 mA)
2
Output Noise (I
OUTFS
= 2 mA)
2
Noise Spectral Density
3
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
f
CLOCK
= 25 MSPS; f
OUT
= 1.00 MHz
0 dBFS Output
−6 dBFS Output
−12 dBFS Output
−18 dBFS Output
f
CLOCK
= 65 MSPS; f
OUT
= 1.00 MHz
f
CLOCK
= 65 MSPS; f
OUT
= 2.51 MHz
f
CLOCK
= 65 MSPS; f
OUT
= 10 MHz
f
CLOCK
= 65 MSPS; f
OUT
= 15 MHz
f
CLOCK
= 65 MSPS; f
OUT
= 25 MHz
f
CLOCK
= 165 MSPS; f
OUT
= 21 MHz
f
CLOCK
= 165 MSPS; f
OUT
= 41 MHz
f
CLOCK
= 210 MSPS; f
OUT
= 41 MHz
f
CLOCK
= 210 MSPS; f
OUT
= 69 MHz
Spurious-Free Dynamic Range Within a Window
f
CLOCK
= 25 MSPS; f
OUT
= 1.00 MHz; 2 MHz Span
f
CLOCK
= 50 MSPS; f
OUT
= 5.02 MHz; 2 MHz Span
f
CLOCK
= 65 MSPS; f
OUT
= 5.03 MHz; 2.5 MHz Span
f
CLOCK
= 125 MSPS; f
OUT
= 5.04 MHz; 4 MHz Span
Total Harmonic Distortion
f
CLOCK
= 25 MSPS; f
OUT
= 1.00 MHz
f
CLOCK
= 50 MSPS; f
OUT
= 2.00 MHz
f
CLOCK
= 65 MSPS; f
OUT
= 2.00 MHz
f
CLOCK
= 125 MSPS; f
OUT
= 2.00 MHz
Signal-to-Noise Ratio
f
CLOCK
= 65 MSPS; f
OUT
= 5 MHz; I
OUTFS
= 20 mA
f
CLOCK
= 65 MSPS; f
OUT
= 5 MHz; I
OUTFS
= 5 mA
f
CLOCK
= 125 MSPS; f
OUT
= 5 MHz; I
OUTFS
= 20 mA
f
CLOCK
= 125 MSPS; f
OUT
= 5 MHz; I
OUTFS
= 5 mA
f
CLOCK
= 165 MSPS; f
OUT
= 5 MHz; I
OUTFS
= 20 mA
f
CLOCK
= 165 MSPS; f
OUT
= 5 MHz; I
OUTFS
= 5 mA
f
CLOCK
= 210 MSPS; f
OUT
= 5 MHz; I
OUTFS
= 20 mA
f
CLOCK
= 210 MSPS; f
OUT
= 5 MHz; I
OUTFS
= 5 mA
Min
210
11
1
5
2.5
2.5
50
30
−155
Typ
Max
Unit
MSPS
ns
ns
pV-s
ns
ns
pA/√Hz
pA/√Hz
dBm/Hz
77
90
87
82
82
85
84
80
75
74
73
60
68
64
90
90
87
87
−86
−77
−77
−77
82
88
77
78
70
70
74
67
−77
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
dB
dB
dB
dB
dB
dB
dB
84
Rev. C | Page 4 of 32
Data Sheet
Parameter
Multitone Power Ratio (8 Tones at 400 kHz Spacing)
f
CLOCK
= 78 MSPS; f
OUT
= 15.0 MHz to 18.2 MHz
0 dBFS Output
−6 dBFS Output
−12 dBFS Output
−18 dBFS Output
1
2
AD9744
Min
Typ
Max
Unit
66
68
62
61
dBc
dBc
dBc
dBc
Measured single-ended into 50 Ω load.
Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.
3
Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.
DIGITAL SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
OUTFS
= 20 mA, unless otherwise noted.
Table 3.
Parameter
DIGITAL INPUTS
1
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
Input Setup Time (t
S
)
Input Hold Time (t
H
)
Latch Pulse Width (t
LPW
)
CLK INPUTS
2
Input Voltage Range
Common-Mode Voltage
Differential Voltage
1
2
Min
2.1
−10
−10
Typ
3
0
Max
Unit
V
V
µA
µA
pF
ns
ns
ns
V
V
V
0.9
+10
+10
5
2.0
1.5
1.5
0
0.75
0.5
3
2.25
1.5
1.5
Includes CLOCK pin on SOIC/TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode.
Applicable to CLK+ and CLK– inputs when configured for differential or PECL clock input mode.
DB0–DB13
t
S
CLOCK
t
H
t
LPW
t
PD
t
ST
Figure 2. Timing Diagram
Rev. C | Page 5 of 32
02913-002
IOUTA
OR
IOUTB
0.1%
0.1%
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