71V67603S150BGGI datasheet, PDF

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71V67603S150BGGI: DescriptionSRAM 9M 3.3V PBSRAM SLOW P/L; Categorystorage; File Size243KB，20 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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SRAM 9M 3.3V PBSRAM SLOW P/L

71V67603S150BGGI Parametric

Parameter Name	Attribute value
Product Category	SRAM
Manufacturer	IDT (Integrated Device Technology, Inc.)
RoHS	Details
Memory Size	9 Mbit
Organization	256 k x 36
Access Time	3.8 ns
Maximum Clock Frequency	150 MHz
Interface Type	Parallel
Supply Voltage - Max	3.465 V
Supply Voltage - Min	3.135 V
Supply Current - Max	325 mA
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 85 C
Mounting Style	SMD/SMT
Package / Case	PBGA-119
Packaging	Tray
Height	2.15 mm
Length	14 mm
Memory Type	SDR
Moisture Sensitive	Yes
Operating Temperature Range	- 40 C to + 85 C
Factory Pack Quantity	84
Type	Synchronous
Width	22 mm

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256K X 36, 512K X 18

IDT71V67603/Z

3.3V Synchronous SRAMs

IDT71V67803/Z

3.3V I/O, Burst Counter

Pipelined Outputs, Single Cycle Deselect

◆

Features

◆

256K x 36, 512K x 18 memory configurations

Supports high system speed:

– 166MHz 3.5ns clock access time

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

LBO

input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte

write enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O supply (V

DDQ

)

Packaged in a JEDEC Standard 100-pin thin plastic quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA).

Description

The IDT71V67603/7803 are high-speed SRAMs organized as

256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write,

data, address and control registers. Internal logic allows the SRAM to

generate a self-timed write based upon a decision which can be left until

the end of the write cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V67603/7803 can provide four cycles of

data for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will be pipelined for one

cycle before it is available on the next rising clock edge. If burst mode

operation is selected (ADV=LOW), the subsequent three cycles of output

data will be available to the user on the next three rising clock edges. The

order of these three addresses are defined by the internal burst counter

and the

LBO

input pin.

The IDT71V67603/7803 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-

pin thin plastic quad flatpack (TQFP), a 119 ball grid array (BGA) and a 165

fine pitch ball grid array (fBGA).

Pin Description Summary

-A

BWE

(1)

CLK

ADV

ADSC

ADSP

LBO

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enable

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

N/A

5310 tbl 01

NOTE:

and

are not applicable for the IDT71V67802.

FEBRUARY 2009

DSC-5310/07

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