Features
•
Low-voltage and Standard-voltage Operation
•
•
•
•
•
•
•
•
•
•
•
•
– 2.7 (V
CC
= 2.7V to 5.5V)
– 1.8 (V
CC
= 1.8V to 3.6V)
Internally Organized 16,384 x 8 and 32,768 x 8
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1 MHz (5V), 400 kHz (2.7V, 2.5V) and 100 kHz (1.8V) Compatibility
Write Protect Pin for Hardware and Software Data Protection
64-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5 ms Max)
High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 40 Years
Extended Temperature and Lead-free/Halogen-free
Devices Available
8-lead JEDEC PDIP, 8-lead JEDEC and EIAJ SOIC, 8-lead MAP, 8-lead TSSOP, 8-lead
SAP and 8-ball dBGA2 Packages
Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
Two-wire Serial
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
Description
The AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable and
programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8
bits each. The device’s cascadable feature allows up to 4 devices to share a common
Two-wire bus. The device is optimized for use in many industrial and commercial appli-
cations where low power and low voltage operation are essential. The devices are
available in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ
SOIC, 8-lead MAP (24C128), 8-lead TSSOP, 8-lead SOIC Array Package and 8-ball
dBGA2 packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and
1.8V (1.8V to 3.6V) versions.
Table 1.
Pin Configuration
Pin Name
Function
AT24C128
(1)
AT24C256
(2)
Notes:
1. Not recommended for
new design; please
refer to AT24C128B
datasheet.
2. Not recommended for
new design; please
refer to AT24C256B
datasheet.
8-lead PDIP
A0
A1
NC
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
8-lead TSSOP
A0
A1
NC
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0 - A1
SDA
SCL
WP
NC
GND
Address Inputs
Serial Data
Serial Clock Input
Write Protect
No Connect
Ground
8-lead SOIC
A0
A1
NC
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
8-lead MAP
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
A0
A1
NC
GND
Bottom View
8-ball dBGA2
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
8-lead SAP
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
A0
A1
NC
GND
A0
A1
NC
GND
Bottom View
Bottom View
0670T–SEEPR–3/07
1
Absolute Maximum Ratings*
Operating Temperature.................................–55° C to +125° C
Storage Temperature ....................................–65° C to +150° C
Voltage on Any Pin
with Respect to Ground .................................... –1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Figure 1.
Block Diagram
2
AT24C128/256
0670T–SEEPR–3/07
AT24C128/256
Pin Description
SERIAL CLOCK (SCL):
The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA):
The SDA pin is bidirectional for serial data transfer. This pin is open-
drain driven and may be wire-ORed with any number of other open-drain or open collector
devices.
DEVICE/ADDRESSES (A1, A0):
The A1 and A0 pins are device address inputs that are hard-
wired or left not connected for hardware compatibility with other AT24CXX devices. When the
pins are hardwired, as many as four 128K/256K devices may be addressed on a single bus
system (device addressing is discussed in detail under the Device Addressing section). If the
pins are left floating, the A1 and A0 pins will be internally pulled down to GND if the capacitive
coupling to the circuit board V
CC
plane is <3 pF. If coupling is >3 pF, Atmel recommends con-
necting the address pins to GND.
WRITE PROTECT (WP):
The write protect input, when connected to GND, allows normal write
operations. When WP is connected high to V
CC
, all write operations to the memory are inhib-
ited. If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive
coupling to the circuit board V
CC
plane is <3 pF. If coupling is >3 pF, Atmel recommends con-
necting the pin to GND.
Memory
Organization
AT24C128/256, 128K/256K SERIAL EEPROM:
The 128K/256K is internally organized as
256/512 pages of 64-bytes each. Random word addressing requires a 14/15-bit data word
address.
3
0670T–SEEPR–3/07
Table 2.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25° C, f = 1.0 MHz, V
CC
= +1.8V.
Symbol
C
I/O
C
IN
Note:
Test Condition
Input/Output Capacitance (SDA)
Input Capacitance (A
0
, A
1
, SCL)
1. This parameter is characterized and is not 100% tested.
Max
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
Table 3.
DC Characteristics
(1)
Applicable over recommended operating range from: T
AI
=
–
40° C to +85° C, V
CC
= +1.8V to +5.5V; T
AE
=
–
40° C to
+125° C
(2)
, V
CC
= +2.7V to +5.5V(unless otherwise noted).
Symbol
V
CC1
V
CC2
V
CC3
I
CC1
I
CC2
I
SB1
Parameter
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current
Supply Current
Standby Current
(1.8V option)
Standby Current
(2.5V option)
Standby Current
(5.0V option)
Input Leakage Current
Output Leakage
Current
Input Low Level
(1)
Input High Level
(1)
Output Low Level
Output Low Level
V
CC
= 3.0V
V
CC
= 1.8V
I
OL
= 2.1 mA
I
OL
= 0.15 mA
V
CC
= 5.0V
V
CC
= 5.0V
V
CC
= 1.8V
V
CC
= 3.6V
V
CC
= 2.5V
V
CC
= 5.5V
V
CC
= 4.5 - 5.5V
V
IN
= V
CC
or V
SS
V
OUT
= V
CC
or V
SS
–0.6
V
CC
x 0.7
READ at 400 kHz
WRITE at 400 kHz
V
IN
= V
CC
or V
SS
Test Condition
Min
1.8
2.5
4.5
1.0
2.0
Typ
Max
3.6
5.5
5.5
2.0
3.0
0.2
2.0
0.5
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
0.10
0.05
6.0
6.0
3.0
3.0
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.2
µA
µA
µA
V
V
V
V
µA
Units
V
V
V
mA
mA
µA
I
SB2
I
SB3
I
LI
I
LO
V
IL
V
IH
V
OL2
V
OL1
Notes:
1. V
IL
min and V
IH
max are reference only and are not tested.
2. The AT24C128/256 bearing the process letter “B” on the package (the mark is located in the lower right corner on the top-
side of the package) are approved for operation in the extended temperature range.
4
AT24C128/256
0670T–SEEPR–3/07
AT24C128/256
Table 4.
AC Characteristics – Industrial Temperatures
Applicable over recommended operating range from T
AI
=
–
40° C to +85° C, V
CC
= +1.8V to +5.5V, CL = 100 pF (unless oth-
erwise noted). Test conditions are listed in Note 2.
1.8-volt
Symbol
f
SCL
t
LOW
t
HIGH
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
(1)
Notes:
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
Time the bus must be free before a
new transmission can start
(1)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time
(1)
Inputs Fall Time
(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
25°C, Page Mode
4.7
100
20
or
5
(3)
4.7
4.0
0.1
4.7
4.0
4.7
0
200
1.0
300
0.6
50
10
or
5
(3)
100k or 1,000,000
(4)
4.5
Min
Max
100
1.3
0.6
0.05
1.3
0.6
0.6
0
100
0.3
300
0.25
50
10
or
5
(3)
0.9
Min
2.5-volt
Max
400
0.4
0.4
0.05
0.5
0.25
0.25
0
100
0.3
100
0.55
Min
5.0-volt
Max
1000
Units
kHz
µs
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
ms
Write
Cycles
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
R
L
(connects to V
CC
): 1.3 kΩ (2.5V, 5V), 10 kΩ (1.8V)
Input pulse voltages: 0.3 V
CC
to 0.7 V
CC
Input rise and fall times:
≤
50 ns
Input and output timing reference voltages: 0.5 V
CC
3. The Write Cycle Time of 5 ms only applies to the AT24C128/256 devices bearing the process letter “B” on the package (the
mark is located in the lower right corner on the top side of the package).
4. The AT24C128/256 bearing the process letter “B” in the package (the mark is located in the lower right corner on the top
side of the package), guarantees 1 million write cycle endurance (1.8 – 3.6V).
5
0670T–SEEPR–3/07
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