FemtoClock
®
NG Octal Universal
Frequency Translator
8T49N282
Datasheet
General Description
The 8T49N282 has two independent, fractional-feedback PLLs that
can be used as jitter attenuators and frequency translators. It is
equipped with six integer and two fractional output dividers, allowing
the generation of up to eight different output frequencies, ranging
from 8kHz to 1GHz. Four of these frequencies are completely
independent of each other and the inputs. The other four are related
frequencies. The eight outputs may select among LVPECL, LVDS or
LVCMOS output levels.
This functionality makes it ideal to be used in any frequency
translation application, including 1G, 10G, 40G and 100G
Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T
G.709 (2009) FEC rates. The device may also behave as a frequency
synthesizer.
The 8T49N282 accepts up to four differential or single-ended input
clocks and a crystal input. Each of the two internal PLLs can lock to
different input clocks which may be of independent frequencies. The
other two input clocks are intended for redundant backup of the
primary clocks and must be related in frequency to their primary.
The device supports hitless reference switching between input
clocks. The device monitors all input clocks for Loss of Signal (LOS),
and generates an alarm when an input clock failure is detected.
Automatic and manual hitless reference switching options are
supported. LOS behavior can be set to support gapped or un-gapped
clocks.
The 8T49N282 supports holdover for each PLL. The holdover has an
initial accuracy of ±50ppB from the point where the loss of all
applicable input reference(s) has been detected. It maintains a
historical average operating point for each PLL that may be returned
to in holdover at a limited phase slope.
The device places no constraints on input to output frequency
conversion, supporting all FEC rates, including the new revision of
ITU-T Recommendation G.709 (2009), most with 0ppm conversion
error.
Each PLL has a register-selectable loop bandwidth from 0.5Hz to
512Hz.
Each output supports individual phase delay settings to allow
output-output alignment.
The device supports Output Enable inputs and Lock, Holdover and
LOS status outputs.
The device is programmable through an I
2
C interface. It also
supports I
2
C master capability to allow the register configuration to
be read from an external EEPROM. The user may select whether the
programming interface uses I
2
C protocols or SPI protocols, however
in SPI mode, read from the external EEPROM is not supported.
Features
•
•
•
•
•
•
Supports SDH/SONET and Synchronous Ethernet clocks
including all FEC rate conversions
Two differential outputs meet jitter limits for 100G Ethernet and
STM-256/OC-768
•
<0.3ps RMS (including spurs): 12kHz to 20MHz
All outputs <0.5ps RMS (including spurs) 12kHz to 20MHz
Operating modes: locked to input signal, holdover and free-run
Initial holdover accuracy of ±50ppb
Accepts up to four LVPECL, LVDS, LVHSTL, HCSL or LVCMOS
input clocks
•
Accepts frequencies ranging from 8kHz up to 875MHz
•
Auto and manual input clock selection with hitless switching
•
Clock input monitoring, including support for gapped clocks
Phase-Slope Limiting and Fully Hitless Switching options to
control output phase transients
Operates from a 10MHz to 40MHz fundamental-mode crystal
Generates eight LVPECL / LVDS or 16 LVCMOS output clocks
•
Output frequencies ranging from 8kHz up to 1.0GHz (diff)
•
Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
Eight General Purpose I/O pins with optional support for status
and control
•
Eight Output Enable control inputs
•
Lock, Holdover and Loss-of-Signal status outputs
Open-drain Interrupt pin
Write-protect pin to prevent configuration registers being altered
Programmable PLL bandwidth settings for each PLL:
•
0.5Hz, 1Hz, 2Hz, 4Hz, 8Hz, 16Hz, 32Hz, 64Hz, 128Hz, 256Hz
or 512Hz
•
Optional Fast Lock function
Programmable output phase delays in steps as small as 16ps
Register programmable through I
2
C / SPI or via external I
2
C
EEPROM
Bypass clock paths for system tests
Power supply modes:
V
CC
/ V
CCA
/ V
CCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V
3.3V / 3.3V / 1.8V (LVCMOS)
2.5V / 2.5V / 3.3V
2.5V / 2.5V / 2.5V
2.5V / 2.5V / 1.8V (LVCMOS)
Power down modes support consumption as low as 1.7W (see
Power Dissipation and Thermal Considerations
section
for
details)
-40°C to 85°C ambient operating temperature
Package: 72QFN, lead-free RoHs (6)
•
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•
•
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•
•
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•
Applications
•
•
•
•
•
OTN or SONET / SDH equipment Line cards (up to OC-192, and
supporting FEC ratios)
OTN de-mapping (Gapped Clock and DCO mode)
Gigabit and Terabit IP switches / routers including support of
Synchronous Ethernet
Wireless base station baseband
Data communications
©2016 Integrated Device Technology, Inc.
1
Revision G, February 2, 2016
8T49N282 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
2
Name
OSCI
I
Type
Description
Crystal Input. Accepts a 10MHz-40MHz reference from a clock oscillator or a
12pF fundamental mode, parallel-resonant crystal. For proper device
functionality, a crystal or external oscillator must be connected to this pin.
Crystal Output. This pin must be connected to a crystal. If an oscillator is
connected to OSCI, then this pin must be left unconnected.
Pulldown
Pullup
Pullup
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Universal
Universal
Universal
Universal
Universal
Universal
Universal
Universal
Pullup
I
2
C lower address bit A0 / SPI interface chip select signal.
I
2
C interface bi-directional Data / SPI interface serial data output signal.
I
2
C interface bi-directional Clock / SPI interface clock input signal.
I
2
C lower address bit A1 / SPI interface serial data input signal.
Serial Interface Mode Selection. LVCMOS Input Levels:
0 = I
2
C Mode
1 = SPI Mode
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 when left floating (set by the internal
pullup and pulldown resistors.)
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 when left floating (set by the internal
pullup and pulldown resistors.)
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 when left floating (set by the internal
pullup and pulldown resistors.)
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 when left floating (set by the internal
pullup and pulldown resistors.)
Output Clock 0. Please refer to the Output Drivers section for more details.
Output Clock 1. Please refer to the Output Drivers section for more details.
Output Clock 2. Please refer to the Output Drivers section for more details.
Output Clock 3. Please refer to the Output Drivers section for more details.
Output Clock 4. Please refer to the Output Drivers section for more details.
Output Clock 5. Please refer to the Output Drivers section for more details.
Output Clock 6. Please refer to the Output Drivers section for more details.
Output Clock 7. Please refer to the Output Drivers section for more details.
Master Reset input. LVTTL / LVCMOS interface levels.
0 = All registers and state machines are reset to their default values
1 = Device runs normally
3
5
16
17
18
32
7
8
9
10
11
12
13
14
63, 62
57, 56
34, 35
28, 29
51, 50
47, 46
43, 42
39, 38
60
OSCO
S_A0 / nCS
SDATA / SDO
SCLK / SCLK
S_A1 / SDI
nI2C_SPI
CLK0
nCLK0
CLK1
nCLK1
CLK2
nCLK2
CLK3
nCLK3
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Q6, nQ6
Q7, nQ7
nRST
O
I
I/O
I/O
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
I
65
nINT
O
Open-drain
with pullup Interrupt output.
Write protect input. LVTTL / LVCMOS interface levels:
0 = Write operations on the serial port will complete normally, but will have no
effect except on interrupt registers
1 = Serial port writes may change any register.
General-purpose input-outputs. LVTTL / LVCMOS Input levels Open-drain
output.Pulled-up with 5.1k resistor to V
CC.
59
nWP
I
Pullup
41, 45,
49, 53,
37, 54,
26, 31
GPIO[7:0]
I/O
Pullup
©2016 Integrated Device Technology, Inc.
4
Revision G, February 2, 2016
8T49N282 Datasheet
Number
69
6, 30, 36,
55, 61,
ePAD
15
22
1
19, 20,
21, 25
66, 70,
71, 72
64
58
33
27
52
48
44
40
68,
67
23,
24
4
Name
PLL_BYP
I
Type
Pulldown
Description
Bypass Selection. Allow input references to bypass both PLLs. LVTTL /
LVCMOS interface levels.
Negative supply voltage. All V
EE
pins and EPAD must be connected before any
positive supply voltage is applied.
Core and digital function supply voltage.
Core and digital functions supply voltage.
Analog function supply voltage for core analog functions.
Analog function supply voltage for analog functions associated with PLL1.
Analog function supply voltage for analog functions associated with PLL0.
High-speed output supply voltage for output pair Q0, nQ0.
High-speed output supply voltage for output pair Q1, nQ1.
High-speed output supply voltage for output pair Q2, nQ2.
High-speed output supply voltage for output pair Q3, nQ3.
High-speed output supply voltage for output pair Q4, nQ4.
High-speed output supply voltage for output pair Q5, nQ5.
High-speed output supply voltage for output pair Q6, nQ6.
High-speed output supply voltage for output pair Q7, nQ7.
PLL0 External Capacitance. A 0.1µF capacitance value across these pins is
recommended.
PLL1 External Capacitance. A 0.1µF capacitance value across these pins is
recommended.
No connect.
V
EE
V
CC
V
CC
V
CCA
V
CCA
V
CCA
V
CCO0
V
CCO1
V
CCO2
V
CCO3
V
CCO4
V
CCO5
V
CCO6
V
CCO7
CAP0,
CAP0_REF
CAP1,
CAP1_REF
nc
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Analog
Analog
Unused
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See
Table 2,
Pin Characteristics,
for typical values.
©2016 Integrated Device Technology, Inc.
5
Revision G, February 2, 2016
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