8-output 1.8V PCIe Gen1-3
Zero-Delay/Fan-out Buffer w/Zo=100ohms
9DBV0841
DATASHEET
Description
The 9DBV0841 is a 1.8V member of IDT's full featured PCIe
family. It has integrated output terminations providing
Zo=100 for direct connection for 100 transmission lines.
The device has 8 output enables for clock management and 3
selectable SMBus addresses.
Features/Benefits
•
LP-HCSL outputs save 32 resistors; minimal board space
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and BOM cost
62mW typical power consumption in PLL mode; eliminates
thermal concerns
Spread Spectrum (SS) compatible; allows use of SS for
EMI reduction
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by
common clock sources
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Software selectable 50MHz or 125MHz PLL operation;
useful for Ethernet applications
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Space saving 48-pin 6x6mm VFQFPN; minimal board
space
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Recommended Application
SSD, microServers, WLAN Access points
Output Features
•
8 – 1-200Hz Low-Power (LP) HCSL DIF pairs
Key Specifications
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DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF
additive
phase jitter is <100fs rms for PCIe Gen3
DIF
additive
phase jitter <300fs rms for 12k-20MHz
Block Diagram
vOE(7:0)#
8
DIF7
DIF6
CLK_IN
CLK_IN#
SS
Compatible
PLL
DIF5
DIF4
DIF3
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
Control
Logic
DIF2
DIF1
DIF0
9DBV0841 APRIL 28, 2016
1
©2016 Integrated Device Technology, Inc.
9DBV0841 DATASHEET
Pin Configuration
^CKPWRGD_PD#
VDD1.8
VDDIO
VDDIO
vOE7#
vOE6#
48 47 46 45 44 43 42 41 40 39 38 37
vSADR_tri 1
^vHIBW_BYPM_LOBW# 2
FB_DNC 3
FB_DNC# 4
VDDR1.8 5
CLK_IN 6
CLK_IN# 7
GNDR 8
GNDDIG 9
SCLK_3.3 10
SDATA_3.3 11
VDDDIG1.8 12
13 14 15 16 17 18 19 20 21 22 23 24
vOE0#
DIF0#
vOE1#
GND
DIF0
DIF1
DIF1#
VDD1.8
DIF2
VDDIO
VDDIO
DIF2#
36 DIF5#
35 DIF5
34 vOE4#
33 DIF4#
vOE5#
32 DIF4
31 VDDIO
30 VDDA1.8
29 GNDA
28 vOE3#
27 DIF3#
26 DIF3
25 vOE2#
DIF7#
DIF6#
9DBV0841
EPAD should be
connected to GND
48-pin VFQFPN, 6x6 mm, 0.4mm pitch
^v
v
^
prefix indicates internal 120KOhm pull up
AND pull
down resistor (biased to VDD/2)
prefix indicates internal 120KOhm pull down resistor
prefix indicates internal 120KOhm pull up resistor
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+
Read/Write bit
x
x
x
Power Management Table
SMBus
DIFx
OEx# Pin
OEx bit
True O/P
Comp. O/P
0
X
X
X
Low
Low
1
Running
0
X
Low
Low
1
Running
1
0
Running
Running
1
Running
1
1
Low
Low
1. If Bypass mode is selected, the PLL will be off, and outputs will be running.
CKPWRGD_PD#
CLK_IN
PLL
Off
On
1
On
1
On
1
Power Connections
Pin Number
VDD
5
12
20, 31, 38
30
13, 21, 31,
39, 47
VDDIO
GND
8
9
22, 29, 40
29
Description
Input
receiver
analog
Digital Power
DIF outputs
PLL Analog
GND
DIF7
DIF6
Frequency Select Table
FSEL
Byte3 [4:3]
00 (Default)
01
10
11
CLK_IN
(MHz)
100.00
50.00
125.00
Reserved
DIFx
(MHz)
CLK_IN
CLK_IN
CLK_IN
Reserved
PLL Operating Mode
HiBW_BypM_LoBW#
0
M
1
MODE
PLL Lo BW
Bypass
PLL Hi BW
Byte1 [7:6]
Readback
00
01
11
Byte1 [4:3]
Control
00
01
11
8-OUTPUT 1.8V PCIE GEN1-3 ZERO-DELAY/FAN-OUT BUFFER W/ZO=100OHMS
2
APRIL 28, 2016
9DBV0841 DATASHEET
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
TYPE
DESCRIPTION
LATCHED
vSADR_tri
Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
IN
LATCHED Trilevel input to select High BW, Bypass or Low BW mode.
^vHIBW_BYPM_LOBW#
IN
See PLL Operating Mode Table for Details.
True clock of differential feedback. The feedback output and feedback input are
FB_DNC
DNC
connected internally on this pin. Do not connect anything to this pin.
Complement clock of differential feedback. The feedback output and feedback
FB_DNC#
DNC
input are connected internally on this pin. Do not connect anything to this pin.
VDDR1.8
CLK_IN
CLK_IN#
GNDR
GNDDIG
SCLK_3.3
SDATA_3.3
VDDDIG1.8
VDDIO
vOE0#
DIF0
DIF0#
vOE1#
DIF1
DIF1#
VDD1.8
VDDIO
GND
DIF2
DIF2#
vOE2#
DIF3
DIF3#
vOE3#
GNDA
VDDA1.8
VDDIO
DIF4
DIF4#
vOE4#
DIF5
DIF5#
vOE5#
VDD1.8
PWR
IN
IN
GND
GND
IN
I/O
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
GND
OUT
OUT
IN
OUT
OUT
IN
GND
PWR
PWR
OUT
OUT
IN
OUT
OUT
IN
PWR
1.8V power for differential input clock (receiver). This VDD should be treated as
an Analog power rail and filtered appropriately.
True Input for differential reference clock.
Complementary Input for differential reference clock.
Analog Ground pin for the differential input (receiver)
Ground pin for digital circuitry
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
1.8V digital power (dirty power)
Power supply for differential outputs
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Power supply, nominal 1.8V
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Ground pin for the PLL core.
1.8V power for the PLL core.
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply, nominal 1.8V
PIN NAME
APRIL 28, 2016
3
8-OUTPUT 1.8V PCIE GEN1-3 ZERO-DELAY/FAN-OUT BUFFER W/ZO=100OHMS
9DBV0841 DATASHEET
Pin Descriptions (cont.)
PIN #
39
40
41
42
43
44
45
46
47
48
49
PIN NAME
VDDIO
GND
DIF6
DIF6#
vOE6#
DIF7
DIF7#
vOE7#
VDDIO
^CKPWRGD_PD#
epad
TYPE
PWR
GND
OUT
OUT
IN
OUT
OUT
IN
PWR
IN
GND
DESCRIPTION
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 6. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 7. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high
assertion. Low enters Power Down Mode, subsequent high assertions exit
Power Down Mode. This pin has internal pull-up resistor.
Connect epad to ground
Test Loads
Low-Power push-pull HCSL Output test load
(integrated terminations)
L inches
Differential Zo
2pF
2pF
L = 5 inches
Alternate Terminations
The 9DBV family can easily drive LVPECL, LVDS, and CML logic. See
“AN-891 Driving LVPECL, LVDS, and CML Logic with
IDT's "Universal" Low-Power HCSL Outputs”
for details.
8-OUTPUT 1.8V PCIE GEN1-3 ZERO-DELAY/FAN-OUT BUFFER W/ZO=100OHMS
4
APRIL 28, 2016
9DBV0841 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBV0841. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
1.8V Supply Voltage
Input Voltage
Input High Voltage, SMBus
Storage Temperature
Junction Temperature
Input ESD protection
1
2
SYMBOL
VDDxx
V
IN
V
IHSMB
Ts
Tj
ESD prot
CONDITIONS
Applies to VDD, VDDA and VDDIO
SMBus clock and data pins
MIN
-0.5
-0.5
-65
TYP
MAX
2.5
V
DD
+0.5V
3.6V
150
125
UNITS NOTES
V
V
V
°C
°C
V
1,2
1, 3
1
1
1
1
Human Body Model
2000
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 2.5V.
Electrical Characteristics–Clock Input Parameters
TA = T
AMB,
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Input Common Mode
Voltage - DIF_IN
Input Swing - DIF_IN
Input Slew Rate - DIF_IN
Input Leakage Current
Input Duty Cycle
Input Jitter - Cycle to Cycle
1
2
SYMBOL
V
COM
V
SWING
dv/dt
I
IN
d
tin
J
DIFIn
CONDITIONS
Common Mode Input Voltage
Differential value
Measured differentially
V
IN
= V
DD ,
V
IN
= GND
Measurement from differential wavefrom
Differential Measurement
MIN
150
300
0.4
-5
45
0
TYP
MAX
1000
UNITS NOTES
mV
mV
1
1
1,2
8
5
55
125
V/ns
uA
%
ps
1
1
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through +/-75mV window centered around differential zero
APRIL 28, 2016
5
8-OUTPUT 1.8V PCIE GEN1-3 ZERO-DELAY/FAN-OUT BUFFER W/ZO=100OHMS
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