Low Skew, 1-to-4 Differential-to-LVDS
Fanout Buffer
8S89832I
Data Sheet
Description
The 8S89832I is a high speed 1-to-4 Differential-to-LVDS Fanout
Buffer. The 8S89832I is optimized for high speed and very low output
skew, making it suitable for use in demanding applications such as
SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The
internally terminated differential input and V
REF
_
AC
pin allow other
differential signal families such as LVPECL, LVDS, and SSTL to be
easily interfaced to the input with minimal use of external
components. The device also has an output enable pin that may be
useful for system test and debug purposes.
The 8S89832I is packaged in a small 3mm x 3mm 16-pin VFQFN
package which makes it ideal for use in space-constrained
applications.
Features
•
•
•
•
•
•
•
•
•
•
•
Four differential LVDS output pairs
IN, nIN input pairs can accept the following differential input levels:
LVPECL, LVDS, SSTL
50 internal input termination to V
T
Maximum output frequency: 2GHz
Output skew: 25ps (maximum)
Part-to-part skew: 200ps (maximum)
Propagation delay: 550ps (maximum)
Additive phase jitter, RMS: 0.09ps (typical)
Full 2.5V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
Q0
nQ0
IN
V
T
nIN
Q2
V
REF_AC
EN
D
CLK
Q
Q3
nQ3
nQ2
50Ω
Pin Assignment
V
DD
GND
nQ0
Q0
Q1 1
nQ1
2
16 15 14 13
12 IN
11 V
T
10 V
REF_AC
9 nIN
5
Q3
Q1
nQ1
50Ω
Q2 3
nQ2 4
6
nQ3
7
V
DD
8
EN
8S89832I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
©2017 Integrated Device Technology, Inc.
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September 22, 2017
8S89832I Data Sheet
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 6
7, 14
Name
Q1, nQ1
Q2, nQ2
Q3, nQ3
V
DD
Output
Output
Output
Power
Type
Description
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Positive supply pins.
Synchronizing clock enable. When LOW, Qx outputs will go LOW and nQx outputs will
go HIGH on the next LOW transition at IN inputs. Input threshold is V
DD
/2V. Includes a
37k
pullup resistor. Default state is HIGH when left floating. The internal latch is
clocked on the falling edge of the input signal IN. See Table 3A
LVTTL / LVCMOS interface levels.
Inverting differential clock input. 50
internal input termination to V
T
.
Reference voltage for AC-coupled applications.
Termination input.
Non-inverting differential clock input. 50
internal input termination to V
T
.
Power supply ground.
Differential output pair. LVDS interface levels.
8
EN
Input
Pullup
9
10
11
12
13
15, 16
nIN
V
REF_AC
V
T
IN
GND
Q0, nQ0
Input
Output
Input
Input
Power
Output
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
37
Maximum
Units
pF
k
©2017 Integrated Device Technology, Inc.
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September 22, 2017
8S89832I Data Sheet
Function Tables
Table 3A. Control Input Function Table
Input
EN
0
1
Q[0:3]
Disabled; LOW
Enabled
Outputs
nQ[0:3]
Disabled; HIGH
Enabled
NOTE: EN switches, the clock outputs are disabled or enabled
following a falling input clock edge as shown in
Figure 1.
Figure 1. EN Timing Diagram
EN
V
DD
/2
t
S
nIN
IN
V
DD
/2
t
H
V
IN
nQx
Qx
→
t
PD
←
V
OD
Table 3B. Truth Table
Inputs
IN
0
1
X
nIN
1
0
X
EN
1
1
0
Outputs
Q[0:3]
0
1
0
(NOTE 1)
nQ[0:3]
1
0
1
(NOTE 1)
NOTE 1: On next negative transition of the input signal (IN).
©2017 Integrated Device Technology, Inc.
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September 22, 2017
8S89832I Data Sheet
Absolute Maximum Ratings
Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Input Current, IN, nIN
V
T
Current, I
VT
Input Sink/Source, I
REF_AC
Operating Temperature Range, T
A
Package Thermal Impedance,
JA
, (Junction-to-Ambient)
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
±50mA
±100mA
± 0.5mA
-40°C to +85°C
74.7C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
95
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
-150
Test Conditions
Minimum
1.7
-0.3
Typical
Maximum
V
DD
+ 0.3
0.7
10
Units
V
V
µA
µA
©2017 Integrated Device Technology, Inc.
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September 22, 2017
8S89832I Data Sheet
Table 4C. Differential DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
I
IN
V
REF_AC
Parameter
Differential Input Resistance
Input High Voltage
Input Low Voltage
Input Voltage Swing; NOTE 1
Differential Input Voltage Swing
Input Current; NOTE 2
Reference Voltage
IN, nIN
V
DD
– 1.40
V
DD
– 1.35
IN, nIN
IN, nIN
IN, nIN
Test Conditions
IN to VT, nIN to VT
Minimum
40
1.2
0
0.15
0.3
35
V
DD
– 1.30
Typical
50
Maximum
60
V
DD
V
IH
– 0.15
1.2
Units
V
V
V
V
mA
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Guaranteed by design.
Table 4D. LVDS DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.125
Test Conditions
Minimum
247
Typical
Maximum
454
50
1.375
50
Units
mV
mV
V
mV
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
f
OUT
t
PD
tsk(o)
tsk(pp)
tjit
t
s
/t
H
t
R
/ t
F
Parameter
Operating Frequency
Propagation Delay; (Differential)
NOTE 1
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
Clock Enable Setup Time
Output Rise/Fall Time
EN to IN, nIN
20% to 80%
200MHz, Integration Range:
12kHz - 20MHz
300
50
235
0.09
300
Test Conditions
Minimum
Typical
Maximum
2
550
25
200
Units
GHz
ps
ps
ps
ps
ps
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
All parameters are measured at
1.5GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
©2017 Integrated Device Technology, Inc.
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September 22, 2017
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