24AA024/24LC024/24AA025/24LC025
2K I
2
C
™
Serial EEPROM
Device Selection Table
Part
Number
24AA024
24AA025
24LC024
24LC025
Note 1:
V
CC
Range
1.7V-5.5V
1.7V-5.5V
2.5V-5.5V
2.5V-5.5V
Max
Clock
400 kHz
(1)
400 kHz
(1)
400 kHz
400 kHz
Temp. Write
Range Protect
I
I
I
I
Yes
No
Yes
No
Description:
The Microchip Technology Inc. 24AA024/24LC024/
24AA025/24LC025 is a 2 Kbit Serial Electrically
Erasable PROM with a voltage range of 1.7V to 5.5V.
The device is organized as a single block of 256 x 8-bit
memory with a 2-wire serial interface. Low current
design permits operation with typical standby and
active currents of only 1
μA
and 1 mA, respectively.
The device has a page write capability for up to 16
bytes of data. Functional address lines allow the
connection of up to eight 24AA024/24LC024/
24AA025/24LC025 devices on the same bus for up to
16K bits of contiguous EEPROM memory. The device
is available in the standard 8-pin PDIP, 8-pin SOIC
(3.90 mm), TSSOP, 2x3 DFN and MSOP packages.
100 kHz for V
CC
< 2.5V
Features:
• Single supply with operation from 1.7V to 5.5V for
24AA024/24AA025 devices, 2.5V for 24LC024/
24LC025 devices
• Low-power CMOS technology:
- Read current 1 mA, typical
- Standby current 1
μA,
typical
• 2-wire serial interface, I
2
C™ compatible
• Cascadable up to eight devices
• Schmitt Trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz and 400 kHz clock compatibility
• Page write time 5 ms maximum
• Self-timed erase/write cycle
• 16-byte page write buffer
• Hardware write-protect on 24XX024 devices
• ESD protection >4,000V
• More than 1 million erase/write cycles
• Data retention >200 years
• Factory programming available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN and MSOP
• Pb-free and RoHS compliant
• Temperature ranges:
- Industrial (I): -40°C to +85°C
Package Types
PDIP, MSOP
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
A0
WP A1
SCL A2
SDA V
SS
DFN
A0
A1
A2
V
SS
Note:
SOIC, TSSOP
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
WP pin is not internally connected on the
24XX025
.
Block Diagram
A0 A1 A2
WP*
HV Generator
Memory
Control
Logic
I/O
Control
Logic
XDEC
EEPROM
Array
SDA SCL
V
CC
V
SS
Write-Protect
Circuitry
YDEC
Sense Amp.
R/W Control
©
2007 Microchip Technology Inc.
DS21210K-page 1
24AA024/24LC024/24AA025/24LC025
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins
......................................................................................................................................................≥
4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
V
CC
= 1.7V to 5.5V
Industrial (I): T
A
= -40°C to +85°C
Symbol
V
IH
V
IL
V
HYS
V
OL
I
LI
I
LO
C
IN
, C
OUT
I
CC
Read
I
CC
Write
I
CCS
Min.
0.7 V
CC
—
0.05 V
CC
—
—
—
—
—
—
—
Max.
—
0.3 V
CC
—
0.40
±1
±1
10
1
3
1
Units
V
V
V
V
μA
μA
pF
mA
mA
μA
—
—
(Note)
I
OL
= 3.0 mA, V
CC
= 4.5V
I
OL
= 2.1 mA, V
CC
= 2.5V
V
IN
= V
SS
or V
CC
V
OUT
= V
SS
or V
CC
V
CC
= 5.0V
(Note)
T
A
= 25°C, F
CLK
= 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 5.5V
V
CC
= 5.5V, SDA = SCL = V
CC
WP = V
SS
, A0, A1, A2 = V
SS
Conditions
All parameters apply across the
specified operating ranges unless
otherwise noted.
Parameter
SCL and SDA pins:
High-level input voltage
Low-level input voltage
Hysteresis of Schmitt Trigger inputs
Low-level output voltage
Input leakage current
Output leakage current
Pin capacitance (all inputs/outputs)
Operating current
Standby current
Note:
This parameter is periodically sampled and not 100% tested.
DS21210K-page 2
©
2007 Microchip Technology Inc.
24AA024/24LC024/24AA025/24LC025
TABLE 1-2:
AC CHARACTERISTICS
V
CC
= 1.7V to 5.5V
Industrial (I): T
A
= -40°C to +85°C
Vcc = 2.5V - 5.5V
FAST MODE
Min.
—
600
1300
—
—
600
600
0
100
600
—
1300
Max.
400
—
—
300
300
—
—
—
—
—
900
—
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
(Note 1)
(Note 1)
After this period the first
clock pulse is generated
Only relevant for repeated
Start condition
(Note 2)
—
—
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1),
C
B
≤
100 pF
(Note 3)
Byte or Page mode
All parameters apply across the specified
operating ranges unless otherwise noted.
STD MODE
Parameter
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Start condition setup time
Data input hold time
Data input setup time
Stop condition setup time
Output valid from clock
Bus free time
Symbol
Min.
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
—
4000
4700
—
—
4000
4700
0
250
4000
—
4700
Max.
100
—
—
1000
300
—
—
—
—
—
3500
—
Units
Remarks
Output fall time from V
IH
minimum to V
IL
maximum
T
OF
—
—
—
1M
250
50
5
—
20 +0.1
C
B
—
—
1M
250
50
5
—
ns
ns
ms
Input filter spike suppression T
SP
(SDA and SCL pins)
Write cycle time
Endurance
Note 1:
2:
3:
4:
T
WC
cycles 25°C,
(Note 4)
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T
SP
and V
HYS
specifications are due to Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be downloaded at
www.microchip.com.
©
2007 Microchip Technology Inc.
DS21210K-page 3
24AA024/24LC024/24AA025/24LC025
FIGURE 1-1:
BUS TIMING DATA
T
F
SCL
T
HIGH
T
R
T
SU
:
STA
T
LOW
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
SDA
IN
T
SP
T
HD
:
STA
T
BUF
T
AA
SDA
OUT
DS21210K-page 4
©
2007 Microchip Technology Inc.
24AA024/24LC024/24AA025/24LC025
2.0
PIN DESCRIPTIONS
Pin Function Table
Name
A0
A1
A2
V
SS
SDA
SCL
WP
V
CC
1
2
3
4
5
6
7
8
PDIP
1
2
3
4
5
6
7
8
SOIC
1
2
3
4
5
6
7
8
TSSOP
1
2
3
4
5
6
7
8
DFN
1
2
3
4
5
6
7
8
MSOP
Description
Address Pin AO
Address Pin A1
Address Pin A2
Ground
Serial Address/Data I/O
Serial Clock
Write-Protect Input
+1.7 to 5.5V Power Supply
2.1
SDA Serial Data
2.5
Noise Protection
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal, therefore, the SDA bus requires a pull-up
resistor to V
CC
(typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
The 24AA024/24LC024/24AA025/24LC025 employs a
V
CC
threshold detector circuit which disables the
internal erase/write logic if the V
CC
is below 1.5 volts at
nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
2.2
SCL Serial Clock
3.0
FUNCTIONAL DESCRIPTION
The SCL input is used to synchronize the data transfer
from and to the device.
2.3
A0, A1, A2
The levels on the A0, A1 and A2 inputs are compared
with the corresponding bits in the slave address. The
chip is selected if the compare is true.
Up to eight 24AA024/24LC024/24AA025/24LC025
devices may be connected to the same bus by using
different Chip Select bit combinations. These inputs
must be connected to either V
CC
or V
SS
.
The 24AA024/24LC024/24AA025/24LC025 supports
a bidirectional, 2-wire bus and data transmission
protocol. A device that sends data onto the bus is
defined as transmitter, while a device receiving data
is defined as receiver. The bus has to be controlled
by a master device which generates the Serial Clock
(SCL), controls the bus access and generates the
Start and Stop conditions, while the 24AA024/
24LC024/24AA025/24LC025 works as slave. Both
master and slave can operate as transmitter or
receiver, but the master device determines which
mode is activated.
2.4
WP (24XX024 Only)
WP is the hardware write-protect pin. It must be tied to
V
CC
or V
SS
. If tied to Vcc, hardware write protection is
enabled. If WP is tied to Vss, the hardware write
protection is disabled. Note that the WP pin is available
only on the 24XX024. This pin is not internally
connected on the 24LC025.
©
2007 Microchip Technology Inc.
DS21210K-page 5
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