D2
PA
K
BUK962R5-60E
N-channel TrenchMOS logic level FET
Rev. 2 — 16 May 2012
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel MOSFET in a SOT404 package using TrenchMOS technology. This
product has been designed and qualified to AEC Q101 standard for use in high
performance automotive applications.
1.2 Features and benefits
AEC Q101 compliant
Repetitive avalanche rated
Suitable for thermally demanding
environments due to 175 °C rating
True logic level gate with VGS(th)
rating of greater than 0.5V at 175 °C
1.3 Applications
12 V Automotive systems
Motors, lamps and solenoid control
Start-Stop micro-hybrid applications
Transmission control
Ultra high performance power
switching
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
drain-source on-state
resistance
gate-drain charge
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
V
GS
= 5 V; T
mb
= 25 °C; see
Figure 1
T
mb
= 25 °C; see
Figure 2
V
GS
= 5 V; I
D
= 25 A; T
j
= 25 °C;
see
Figure 11
V
GS
= 5 V; I
D
= 25 A; V
DS
= 48 V;
see
Figure 13;
see
Figure 14
[1]
Min
-
-
-
-
Typ
-
-
-
2
Max
60
120
357
2.5
Unit
V
A
W
mΩ
Static characteristics
Dynamic characteristics
Q
GD
-
41.2
-
nC
[1]
Continuous current is limited by package.
NXP Semiconductors
BUK962R5-60E
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G
D
S
D
gate
drain
source
mounting base;
connected to drain
2
1
3
mb
D
Simplified outline
Graphic symbol
G
mbb076
S
SOT404 (D2PAK)
3. Ordering information
Table 3.
Ordering information
Package
Name
BUK962R5-60E
D2PAK
Description
plastic single-ended surface-mounted package (D2PAK);
3 leads (one lead cropped)
Version
SOT404
Type number
4. Marking
Table 4.
Marking codes
Marking code
BUK962R5-60E
Type number
BUK962R5-60E
BUK962R5-60E
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 16 May 2012
2 of 14
NXP Semiconductors
BUK962R5-60E
N-channel TrenchMOS logic level FET
5. Limiting values
Table 5.
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive drain-source
avalanche energy
T
mb
= 25 °C
pulsed; t
p
≤
10 µs; T
mb
= 25 °C
I
D
= 120 A; V
sup
≤
60 V; R
GS
= 50
Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped;
see
Figure 3
[2][3]
[1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
R
GS
= 20 kΩ
DC
Pulsed
T
mb
= 25 °C; V
GS
= 5 V; see
Figure 1
T
mb
= 100 °C; V
GS
= 5 V; see
Figure 1
T
mb
= 25 °C; pulsed; t
p
≤
10 µs;
see
Figure 4
T
mb
= 25 °C; see
Figure 2
[1]
[1]
Min
-
-
-10
-15
-
-
-
-
-55
-55
-
-
-
Max
60
60
10
15
120
120
1019
357
175
175
120
1019
655
Unit
V
V
V
V
A
A
A
W
°C
°C
A
A
mJ
Source-drain diode
Avalanche ruggedness
[1]
[2]
[3]
Continuous current is limited by package.
Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
Refer to application note AN10273 for further information.
BUK962R5-60E
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 16 May 2012
3 of 14
NXP Semiconductors
BUK962R5-60E
N-channel TrenchMOS logic level FET
300
I
D
(A)
240
003aag344
120
P
der
(%)
80
03aa16
180
(1)
120
40
60
0
0
50
100
150
T
mb
(
°
C)
200
0
0
50
100
150
T
mb
(°C)
200
(1) Capped at 120A due to package
Fig 1.
Continuous drain current as a function of
mounting base temperature
10
3
I
AL
(A)
10
2
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
003aag355
(1)
10
(2)
1
(3)
10
-1
10
-3
10
-2
10
-1
1
t
AL
(ms)
10
Fig 3.
Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time
BUK962R5-60E
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 16 May 2012
4 of 14
NXP Semiconductors
BUK962R5-60E
N-channel TrenchMOS logic level FET
10
4
I
D
(A)
10
3
Limit R
DSon
= V
DS
/ I
D
t
p
=10
μ
s
10
2
100
μ
s
003aag345
10
DC
1
1 ms
10 ms
100 ms
10
2
10
3
10
-1
10
-1
1
10
V
DS
(V)
Fig 4.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
6. Thermal characteristics
Table 6.
Symbol
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from
junction to mounting base
thermal resistance from
junction to ambient
Conditions
see
Figure 5
minimum footprint; mounted on
a printed-circuit board
Min
-
-
Typ
-
50
Max
0.42
-
Unit
K/W
K/W
1
Z
th(j-mb)
(K/W)
10
-1
003aaf570
= 0.5
0.2
0.1
0.05
10
-2
P
t
p
T
0.02
t
p
t
T
single shot
10
-3
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s)
1
Fig 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration.
BUK962R5-60E
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 16 May 2012
5 of 14
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