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S71PL127JA0: DescriptionSTACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM; File Size2MB，196 Pages; ManufacturerSPANSION; Websitehttp://www.spansion.com/

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S71PL127JA0 Overview

STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM

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S71PL254/127/064/032J based MCPs

Stacked Multi-Chip Product (MCP) Flash Memory and RAM

256M/128/64/32 Megabit (16/8/4/2M x 16-bit) CMOS 3.0 Volt-only

Simultaneous Operation Page Mode Flash Memory and

64/32/16/8/4 Megabit (4M/2M/1M/512K/256K x 16-bit) Static

RAM/Pseudo Static RAM

Datasheet

Distinctive Characteristics

MCP Features

Power supply voltage of 2.7 to 3.1 volt

High performance

— 55 ns

— 65 ns (65 ns Flash, 70ns pSRAM)

Packages

— 7 x 9 x 1.2mm 56 ball FBGA

— 8 x 11.6 x 1.2mm 64 ball FBGA

— 8 x 11.6 x 1.4mm 84 ball FBGA

Operating Temperature

— –25°C to +85°C

— –40°C to +85°C

ADVANCE

General Description

The S71PL series is a product line of stacked Multi-Chip Product (MCP) packages

and consists of:

One or more S29PL (Simultaneous Read/Write) Flash memory die

pSRAM or SRAM

The 256Mb Flash memory consists of two S29PL127J devices. In this case, CE#f2

is used to access the second Flash and no extra address lines are required.

The products covered by this document are listed in the table below:

Flash Memory Density

32Mb

4Mb

8Mb

pSRAM

Density

16Mb

32Mb

64Mb

S71PL032J40

S71PL032J80

S71PL032JA0

S71PL064J80

S71PL064JA0

S71PL064JB0

S71PL127JA0

S71PL127JB0

S71PL127JC0

S71PL254JB0

S71PL254JC0

64Mb

128Mb

256Mb

Flash Memory Density

32Mb

SRAM Density (Note)

4Mb

8Mb

S71PL032J04

S71PL032J08

S71PL064J08

64Mb

Note:

Not recommended for new designs; use pSRAM based MCPs instead.

Publication Number

S71PL254/127/064/032J_00

Revision

Amendment

Issue Date

November 22, 2004

A d v a n c e

I n f o r m a t i o n

S71PL254/127/064/032J based MCPs

Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1

MCP Features ........................................................................................................ 1

General Description . . . . . . . . . . . . . . . . . . . . . . . . 1

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2

32Mb Flash Memory .............................................................................................2

64Mb Flash Memory .............................................................................................2

128Mb Flash Memory ...........................................................................................3

256Mb Flash Memory (2xS29PL127J) ...............................................................3

Table 8. Autoselect Codes (High Voltage Method) .................. 49

Table 9. PL127J Boot Sector/Sector Block Addresses for Protection/

Unprotection ..................................................................... 50

Table 10. PL064J Boot Sector/Sector Block Addresses for

Protection/Unprotection ...................................................... 51

Table 11. PL032J Boot Sector/Sector Block Addresses for

Protection/Unprotection ...................................................... 52

Selecting a Sector Protection Mode ............................................................. 52

Table 12. Sector Protection Schemes ................................... 53

Connection Diagram (S71PL032J)

Connection Diagram (S71PL064J)

Connection Diagram (S71PL127J)

Connection Diagram (S71PL254J)

. . . . . . . . . . . . . .9

. . . . . . . . . . . . . 10

. . . . . . . . . . . . . 11

. . . . . . . . . . . . . 12

Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 53

Sector Protection Schemes . . . . . . . . . . . . . . . . . 53

Password Sector Protection ........................................................................... 53

WP# Hardware Protection ............................................................................. 53

Selecting a Sector Protection Mode ............................................................. 53

Special Handling Instructions For FBGA Package ................................. 12

Persistent Sector Protection . . . . . . . . . . . . . . . . 54

Persistent Protection Bit (PPB) ...................................................................... 54

Persistent Protection Bit Lock (PPB Lock) ................................................. 54

Persistent Sector Protection Mode Locking Bit ....................................... 56

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 14

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . .20

TLC056—56-ball Fine-Pitch Ball Grid Array (FBGA)

9 x 7mm Package ................................................................................................ 20

TSC056—56-ball Fine-Pitch Ball Grid Array (FBGA)

9 x 7mm Package ................................................................................................. 21

TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA)

8 x 11.6mm Package ............................................................................................ 22

TSB064—64-ball Fine-Pitch Ball Grid Array (FBGA)

8 x 11.6 mm Package ...........................................................................................23

FTA084—84-ball Fine-Pitch Ball Grid Array (FBGA)

8 x 11.6mm ............................................................................................................ 24

Password Protection Mode . . . . . . . . . . . . . . . . . 56

Password and Password Mode Locking Bit ................................................ 56

64-bit Password .................................................................................................. 57

Write Protect (WP#) ....................................................................................... 57

Persistent Protection Bit Lock ................................................................... 57

High Voltage Sector Protection .....................................................................58

Figure 1. In-System Sector Protection/Sector Unprotection

Algorithms........................................................................ 59

Temporary Sector Unprotect ........................................................................60

Figure 2. Temporary Sector Unprotect Operation ................... 60

S29PL127J/S29PL064J/S29PL032J for MCP

General Description . . . . . . . . . . . . . . . . . . . . . . . 27

Simultaneous Read/Write Operation with Zero Latency ......................27

Page Mode Features ...........................................................................................27

Standard Flash Memory Features ...................................................................27

Secured Silicon Sector Flash Memory Region ...........................................60

Factory-Locked Area (64 words) ...............................................................61

Customer-Lockable Area (64 words) .......................................................61

Secured Silicon Sector Protection Bits .....................................................61

Figure 3. Secured Silicon Sector Protect Verify ...................... 62

Product Selector Guide . . . . . . . . . . . . . . . . . . . . .29

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Simultaneous Read/Write Block Diagram . . . . . . 31

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 33

Table 1. PL127J Device Bus Operations ................................ 33

Hardware Data Protection .............................................................................62

Low VCC Write Inhibit ................................................................................62

Write Pulse “Glitch” Protection ...............................................................62

Logical Inhibit ...................................................................................................62

Power-Up Write Inhibit ...............................................................................62

Common Flash Memory Interface (CFI) . . . . . . 63

Table 13. CFI Query Identification String .............................. 63

Table 14. System Interface String ........................................ 64

Table 15. Device Geometry Definition ................................... 64

Table 16. Primary Vendor-Specific Extended Query ................ 65

Command Definitions . . . . . . . . . . . . . . . . . . . . . 66

Reading Array Data ...........................................................................................66

Reset Command .................................................................................................66

Autoselect Command Sequence .................................................................... 67

Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Se-

quence .................................................................................................................... 67

Word Program Command Sequence ........................................................... 67

Unlock Bypass Command Sequence ........................................................68

Figure 4. Program Operation ............................................... 69

Requirements for Reading Array Data .........................................................33

Random Read (Non-Page Read) ................................................................33

Page Mode Read ..............................................................................................34

Table 2. Page Select .......................................................... 34

Simultaneous Read/Write Operation ...........................................................34

Table 3. Bank Select .......................................................... 34

Writing Commands/Command Sequences .................................................35

Accelerated Program Operation ...............................................................35

Autoselect Functions .....................................................................................35

Standby Mode .......................................................................................................35

Automatic Sleep Mode ......................................................................................36

RESET#: Hardware Reset Pin .........................................................................36

Table 4. PL127J Sector Architecture ..................................... 37

Table 5. PL064J Sector Architecture ..................................... 44

Table 6. PL032J Sector Architecture ..................................... 47

Table 7. Secured Silicon Sector Addresses ............................ 48

Chip Erase Command Sequence ...................................................................69

Sector Erase Command Sequence ................................................................70

Figure 5. Erase Operation ................................................... 71

Erase Suspend/Erase Resume Commands ................................................... 71

Command Definitions Tables ......................................................................... 72

Table 17. Memory Array Command Definitions ...................... 72

Table 18. Sector Protection Command Definitions .................. 73

Write Operation Status . . . . . . . . . . . . . . . . . . . . 74

DQ7: Data# Polling ............................................................................................ 75

Autoselect Mode ................................................................................................ 49

S71PL254/127/064/032J_00_A6 November 22, 2004

A d v a n c e

I n f o r m a t i o n

Figure 6. Data# Polling Algorithm......................................... 76

RY/BY#: Ready/Busy# .......................................................................................76

DQ6: Toggle Bit I ................................................................................................76

Figure 7. Toggle Bit Algorithm.............................................. 78

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 99

Power Up ..............................................................................................................99

Figure 23. Power Up 1 (CS1# Controlled) ............................. 99

Figure 24. Power Up 2 (CS2 Controlled)................................ 99

DQ2: Toggle Bit II .............................................................................................. 78

Reading Toggle Bits DQ6/DQ2 ..................................................................... 78

DQ5: Exceeded Timing Limits ........................................................................79

DQ3: Sector Erase Timer .................................................................................79

Table 19. Write Operation Status ......................................... 80

Functional Description . . . . . . . . . . . . . . . . . . . . . 100

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 100

DC Recommended Operating Conditions . . . . . 100

DC and Operating Characteristics . . . . . . . . . . . 101

Common ...............................................................................................................101

16M pSRAM ..........................................................................................................102

32M pSRAM .........................................................................................................102

64M pSRAM .........................................................................................................103

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . 81

Figure 8. Maximum Overshoot Waveforms............................. 81

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .82

Industrial (I) Devices ......................................................................................... 82

Wireless Devices ............................................................................................... 82

Supply Voltages ................................................................................................... 82

AC Operating Conditions . . . . . . . . . . . . . . . . . . 103

Test Conditions (Test Load and Test Input/Output Reference) ........103

Figure 25. Output Load .................................................... 103

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .83

Table 20. CMOS Compatible ................................................ 83

AC Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . .84

Test Conditions .................................................................................................. 84

Figure 9. Test Setups......................................................... 84

Table 21. Test Specifications ............................................... 84

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 105

Read Timings .......................................................................................................105

Figure 26. Timing Waveform of Read Cycle(1) ..................... 105

Figure 27. Timing Waveform of Read Cycle(2) ..................... 105

Figure 28. Timing Waveform of Read Cycle(2) ..................... 105

ACC Characteristics (Ta = -40°C to 85°C, V

= 2.7 to 3.1 V) ........104

Switching Waveforms ....................................................................................... 85

Table 22. Key to Switching Waveforms ................................. 85

Figure 10. Input Waveforms and Measurement Levels............. 85

Write Timings .....................................................................................................106

Figure 29. Write Cycle #1 (WE# Controlled)........................

Figure 30. Write Cycle #2 (CS1# Controlled) ......................

Figure 31. Timing Waveform of Write Cycle(3)

(CS2 Controlled) .............................................................

Figure 32. Timing Waveform of Write Cycle(4) (UB#, LB#

Controlled) .....................................................................

106

107

VCC RampRate .................................................................................................. 85

Read Operations ................................................................................................ 86

Table 23. Read-Only Operations .......................................... 86

Figure 11. Read Operation Timings ....................................... 86

Figure 12. Page Read Operation Timings ............................... 87

Reset ...................................................................................................................... 87

Table 24. Hardware Reset (RESET#) .................................... 87

Figure 13. Reset Timings..................................................... 88

pSRAM Type 3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 109

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 30. DC Recommended Operating Conditions ............... 109

Table 31. DC Characteristics (T

= -25°C to 85°C, VDD = 2.6 to

3.3V) ............................................................................. 110

Erase/Program Operations ............................................................................. 89

Table 25. Erase and Program Operations .............................. 89

Timing Diagrams ................................................................................................. 90

Figure 14. Program Operation Timings .................................. 90

Figure 15. Accelerated Program Timing Diagram .................... 90

Figure 16. Chip/Sector Erase Operation Timings ..................... 91

Figure 17. Back-to-back Read/Write Cycle Timings ................. 91

Figure 18. Data# Polling Timings

(During Embedded Algorithms) ............................................ 92

Figure 19. Toggle Bit Timings (During Embedded Algorithms) .. 92

Figure 20. DQ2 vs. DQ6 ...................................................... 93

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 32. AC Characteristics and Operating Conditions (T

= -25°C

to 85°C, V

= 2.6 to 3.3V) .............................................. 110

Table 33. AC Test Conditions ............................................. 111

Figure 33. AC Test Loads .................................................. 111

Figure 34. State Diagram ................................................. 112

Table 34. Standby Mode Characteristics .............................. 112

Protect/Unprotect . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 26. Temporary Sector Unprotect ................................. 93

Figure 21. Temporary Sector Unprotect Timing Diagram.......... 93

Figure 22. Sector/Sector Block Protect and Unprotect Timing

Diagram............................................................................ 94

Controlled Erase Operations ..........................................................................95

Table 27. Alternate CE# Controlled Erase and

Program Operations ........................................................... 95

Table 28. Alternate CE# Controlled Write (Erase/Program)

Operation Timings ............................................................. 96

Table 29. Erase And Programming Performance .................... 97

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 35. Read Cycle 1—Addressed Controlled ...................

Figure 36. Read Cycle 2—CS1# Controlled..........................

Figure 37. Write Cycle 1—WE# Controlled ..........................

Figure 38. Write Cycle 2—CS1# Controlled .........................

Figure 39. Write Cycle3—UB#, LB# Controlled ....................

Figure 40. Deep Power-down Mode ....................................

Figure 41. Power-up Mode ................................................

Figure 42. Abnormal Timing ..............................................

112

113

114

115

BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . 97

Type 2 pSRAM

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Product Information . . . . . . . . . . . . . . . . . . . . . . .

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . .

pSRAM Type 4

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Functional Description . . . . . . . . . . . . . . . . . . . . . 116

Product Portfolio ................................................................................................116

Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . 117

November 22, 2004 S71PL254/127/064/032J_00_A6

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