TC58DVM92A1FTI0
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
512-MBIT (64M
DESCRIPTION
8 BITS) CMOS NAND E PROM
2
The device is a single 3.3 V 512-Mbit (553,648,128) bit NAND Electrically Erasable and Programmable Read-Only
Memory (NAND E
2
PROM) organized as 528 bytes 32 pages 4096 blocks. The device has a 528-byte static register
which allows program and read data to be transferred between the register and the memory cell array in 528-byte
increments. The Erase operation is implemented in a single block unit (16 Kbytes 512 bytes: 528 bytes 32 pages).
The device is a serial-type memory device which utilizes the I/O pins for both address and data input/output as
well as for command inputs. The Erase and Program operations are automatically executed making the device most
suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and
other systems which require high-density non-volatile memory data storage.
FEATURES
Organization
Memory cell allay 528 128K 8
Register
528 8
Page size
528 bytes
Block size
(16K 512) bytes
Modes
Read, Reset, Auto Page Program,
Auto Block Erase, Status Read,
Multi Block Program, Multi Block Erase
Mode control
Serial input/output
Command control
Power supply
V
CC
2.7 V to 3.6 V
Program/Erase Cycles 1E5 cycle (with ECC)
Access time
Cell array to register 25 s max
Serial Read Cycle
50 ns min
Operating current
Read (50 ns cycle)
10 mA typ.
Program (avg.)
10 mA typ.
Erase (avg.)
10 mA typ.
Standby
50 A max.
Package
TSOPI48-P-1220-0.50 (Weight: 0.53g typ.)
PIN ASSIGNMENT
(TOP VIEW)
NC
NC
NC
NC
NC
GND
RY / BY
PIN NAMES
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
NC
NC
I/O8
I/O7
I/O6
I/O5
NC
NC
NC
V
CC
V
SS
NC
NC
NC
I/O4
I/O3
I/O2
I/O1
NC
NC
NC
NC
I/O1 to I/O8
I/O port
RE
CE
NC
NC
V
CC
V
SS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CE
WE
RE
CLE
ALE
WP
RY/BY
GND
V
CC
V
SS
Chip enable
Write enable
Read enable
Command latch enable
Address latch enable
Write protect
Ready/Busy
Ground input
Power supply
Ground
000707EBA1
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide
for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
The products described in this document are subject to the foreign exchange and foreign trade laws.
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
The information contained herein is subject to change without notice.
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TC58DVM92A1FTI0
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta
- 40° to 85°C, V
CC
2.7 V to 3.6 V)
PARAMETER
CLE Setup Time
CLE Hold Time
CE
Setup Time
CE
Hold Time
SYMBOL
t
CLS
t
CLH
t
CS
t
CH
t
WP
t
ALS
t
ALH
t
DS
t
DH
t
WC
t
WH
t
WW
t
RR
t
RP
t
RC
t
REA
t
CEA
t
ALEA
t
CEH
t
REAID
t
OH
t
RHZ
t
CHZ
t
REH
t
IR
t
RSTO
t
CSTO
t
RHW
t
WHC
t
WHR
t
R
t
WB
t
AR2
t
RB
t
CRY
t
RST
MIN
0
10
0
10
25
0
10
20
10
50
15
100
20
35
50
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
Write Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
WE
High Hold Time
WP
High to
WE
Low
Ready to
RE
Falling Edge
Read Pulse Width
Read Cycle Time
RE
Access Time (Serial Data Access)
CE
Access Time (Serial Data Access, ID Read)
35
45
45
100
35
10
30
20
15
0
35
45
0
30
30
25
200
50
200
1
t
r
(
RY/BY
)
6/10/500
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
ns
ns
ns
s
s
(1) (2)
(2)
ALE Access Time (ID Read)
CE
High Time for Last Address in Serial Read Cycle
RE
Access Time (ID Read)
Data Output Hold Time
RE
High to Output High Impedance
CE
High to Output High Impedance
RE
High Hold Time
Output-High-impedance-to-
RE
Falling Edge
RE
Access Time (Status Read)
CE
Access Time (Status Read)
RE
High to
WE
Low
WE
High to
CE
Low
WE
High to
RE
Low
Memory Cell Array to Starting Address
WE
High to Busy
ALE Low to
RE
Low (Read Cycle)
RE
Last Clock Rising Edge to Busy (in Sequential Read)
CE
High to Ready (When interrupted by
CE
in Read Mode)
Device Reset Time (Read/Program/Erase)
AC TEST CONDITIONS
PARAMETER
Input level
Input pulse rise and fall time
Input comparison level
Output data comparison level
Output load
CONDITION
2.4 V, 0.4 V
3 ns
1.5 V, 1.5 V
1.5 V, 1.5 V
C
L
(100 pF)
1 TTL
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TC58DVM92A1FTI0
Note: (1)
CE
High to Ready time depends on the pull-up resistor tied to the
RY/ BY
pin.
(Refer to Application Note (9) toward the end of this document.)
(2) Sequential Read is terminated when t
CEH
is greater than or equal to 100 ns. If the
RE
to
CE
delay
is less than 30 ns,
RY/ BY
signal stays Ready.
t
CEH
100 ns
*
*
: V
IH
or V
IL
CE
RE
525
526
527
A
A : 0 to 30 ns
Busy signal is not output.
RY/BY
Busy
t
CRY
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta
- 40° to 85°C, V
CC
SYMBOL
t
PROG
t
DBSY
t
MBPBSY
N
t
BERASE
2.7 V to 3.6 V)
PARAMETER
MIN
TYP.
200
2
200
MAX
1000
10
1000
3
2
10
ms
UNIT
s
s
s
(1)
NOTES
Programming Time
Dummy Busy Time for Multi Block
Programming
Multi Block Program Busy Time
Number of Programming Cycles on Same
Page
Block Erasing Time
(1): Refer to Application Note (12) toward the end of this document.
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Embedded System
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