IDT72V285L20TFI datasheet, PDF

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IDT72V285L20TFI: Description32K X 18 OTHER FIFO, 10 ns, PQFP64; Categorystorage; File Size206KB，25 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT72V285L20TFI Overview

32K X 18 OTHER FIFO, 10 ns, PQFP64

IDT72V285L20TFI Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	64
Maximum operating temperature	70 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	3.6 V
Minimum supply/operating voltage	3 V
Rated supply voltage	3.3 V
maximum access time	10 ns
Processing package description	PLASTIC, TQFP-64
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	FLATPACK, LOW PROFILE
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.8000 mm
terminal coating	TIN LEAD
Terminal location	QUAD
Packaging Materials	PLASTIC/EPOXY
Temperature level	COMMERCIAL
memory width	18
organize	32K X 18
storage density	589824 deg
operating mode	SYNCHRONOUS
Number of digits	32768 words
Number of digits	32K
cycle	15 ns
Output enable	Yes
Memory IC type	OTHER FIFO

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3.3 VOLT CMOS SuperSync FIFO™

32,768 X 18

65,536 X 18

•

IDT72V275

IDT72V285

.EATURES:

Choose among the following memory organizations:

IDT72V275

32,768 x 18

IDT72V285

65,536 x 18

Pin-compatible with the IDT72V255/72V265 SuperSync FIFOs

10ns read/write cycle time (6.5ns access time)

Fixed, low first word data latency time

Auto power down minimizes standby power consumption

Master Reset clears entire FIFO

Partial Reset clears data, but retains programmable

settings

Retransmit operation with fixed, low first word data

latency time

Empty, Full and Half-Full flags signal FIFO status

Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of two preselected offsets

Program partial flags by either serial or parallel means

Select IDT Standard timing (using

and

flags) or First Word

Fall Through timing (using

and

flags)

Output enable puts data outputs into high impedance state

Easily expandable in depth and width

Independent Read and Write clocks (permit reading and writing

simultaneously)

Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin

•

Slim Thin Quad Flat Pack (STQFP)

High-performance submicron CMOS technology

Industrial temperature range (-40°C to +85°C) is available

•

DESCRIPTION:

The IDT72V275/72V285 are exceptionally deep, high speed, CMOS

First-In-First-Out (FIFO) memories with clocked read and write controls.

These FIFOs offer numerous improvements over previous SuperSync

FIFOs, including the following:

•

The limitation of the frequency of one clock input with respect to the other

has been removed. The Frequency Select pin (FS) has been removed,

thus it is no longer necessary to select which of the two clock inputs, RCLK

or WCLK, is running at the higher frequency.

•

The period required by the retransmit operation is now fixed and short.

•

The first word data latency period, from the time the first word is written to

an empty FIFO to the time it can be read, is now fixed and short. (The

variable clock cycle counting delay associated with the latency period

found on previous SuperSync devices has been eliminated on this

SuperSync family.)

SuperSync FIFOs are particularly appropriate for network, video, telecom-

munications, data communications and other applications that need to buffer

large amounts of data.

.UNCTIONAL BLOCK DIAGRAM

WEN

WCLK

-D

LD SEN

INPUT REGISTER

OFFSET REGISTER

FF/IR

PAF

EF/OR

PAE

FWFT/SI

WRITE CONTROL

LOGIC

RAM ARRAY

32,768 x 18

65,536 x 18

FLAG

LOGIC

WRITE POINTER

READ POINTER

OUTPUT REGISTER

MRS

PRS

READ

CONTROL

LOGIC

RESET

LOGIC

RCLK

REN

-Q

4512 drw 01

SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES



2001

Integrated Device Technology, Inc.

APRIL 2001

DSC-4512/1

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