TM
ACS161MS
Radiation Hardened
4-Bit Synchronous Counter
Pinouts
16 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835, DESIGNATOR CDIP2-T16,
LEAD FINISH C
TOP VIEW
MR 1
CP 2
P0 3
P1 4
P2 5
P3 6
PE 7
GND 8
16 VCC
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 TE
9 SPE
January 1996
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96706 and Intersil’ QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day
(Typ)
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
2
/mg
• Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability . . . . . . . . . . . >10
12
RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current
≤
1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 21ns (Max), 14ns (Typ)
16 PIN CERAMIC FLATPACK
MIL-STD-1835, DESIGNATOR CDFP4-F16,
LEAD FINISH C
TOP VIEW
MR
CP
P0
P1
P2
P3
PE
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
TC
Q0
Q1
Q2
Q3
TE
SPE
Description
The Intersil ACS161MS is a Radiation Hardened 4-Bit Binary Synchronous
Counter. The MR is an active low master reset. SPE is an active low
Synchronous Parallel Enable which disables counting and allows data at the
preset inputs (P0 - P3) to load the counter. CP is the positive edge clock. TC is
the terminal count or carry output. Both TE and PE must be high for counting
to occur, but are irrelevant to loading. TE low will keep TC low.
The ACS161MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic family.
The ACS161MS is supplied in a 16 lead Ceramic Flatpack (K suffix) or a
Ceramic Dual-In-Line Package (D suffix).
Ordering Information
PART NUMBER
5962F9670601VEC
5962F9670601VXC
ACS161D/Sample
ACS161K/Sample
ACS161HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
25
o
C
25
o
C
25
o
C
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
Spec Number
518818
FN3600.1
ACS161MS
Functional Diagram
SPE
CP
J
CP
K
Q
QN
CD
Q0
P0
MR
J
CP
P1
K
QN
CD
Q
Q1
J
CP
P2
K
Q
QN
CD
Q2
J
CP
K
P3
Q
QN
CD
Q3
PE
TC
TE
TRUTH TABLE
INPUTS
OPERATING MODE
Reset (Clear)
Parallel Load
MR
L
H
H
Count
Inhibit
H
H
H
X
X
CP
X
PE
X
X
X
h
I (Note 2)
X
TE
X
X
X
h
X
I (Note 2)
SPE
X
I
I
h (Note 3)
h (Note 3)
h (Note 3)
P
N
X
I
h
X
X
X
OUTPUTS
Q
N
L
L
H
count
q
N
q
N
TC
L
L
(Note 1)
(Note 1)
(Note 1)
L
H = High Steady State, L = Low Steady State, h = High voltage level one setup time prior to the Low-to-High clock transition, I = Low volt-
age level one setup time prior to the Low-to-High clock transition, X = Don’t Care,q = Lower case letters indicate the state of the referenced
output prior to the Low-to-High clock transition,
= Low-to-High Transition.
NOTES:
1. The TC output is High when TE is High and the counter is at Terminal Count (HHHH).
2. The High-to-Low transition of PE or TE should only occur while ZCP is High for conventional operation.
3. The Low-to-High transition of SPE should only occur while CP is High for conventional operation.
4. The TC output is High when TE is High and the counter is at Terminal Count (HHHH).
Spec Number
2
518818
ACS161MS
Metallization Mask Layout
ACS161MS
CP
(2)
MR
(1)
VCC
(16)
TC
(15)
P0 (3)
(14) Q0
P1 (4)
(13) Q1
P2 (5)
(12) Q2
P3 (6)
(11) Q3
(7)
PE
(8)
GND
(9)
SPE
(10)
TE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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NORTH AMERICA
Intersil Corporation
7585 Irvine Center Drive
Suite 100
Irvine, CA 92618
TEL: (949) 341-7000
FAX: (949) 341-7123
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2401 Palm Bay Rd.
Palm Bay, FL 32905
TEL: (321) 724-7000
FAX: (321) 724-7946
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1006 Lausanne
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Unit 1804 18/F Guangdong Water Building
83 Austin Road
TST, Kowloon Hong Kong
TEL: +852 2723 6339
FAX: +852 2730 1433
Spec Number
4
518818
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