Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
Utilizes industry standard 8M x 16 Sy nchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
144-pin (72-pin dual in-line package)
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH8S64AQFC is 8388608 - word by 64-bit
Synchronous DRAM module. This consists of four
industry standard 8Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
for easy interchange or addition of modules.
single 3.3V±0.3V power supply
Max. Clock frequency -6:133MHz,-7,8:100MHz
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
FEATURES
Frequency
-6,-6L
-7,-7L
-8,-8L
133MHz
100MHz
100MHz
CLK Access Time
(Component SDRAM)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
5.4ns(CL=3)
6.0ns(CL=2)
6.0ns(CL=3)
APPLICATION
main memory or graphic memory in computer systems
PCB Outline
(Front)
(Back)
1
2
143
144
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ELECTRIC
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22.Sep.2000
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
PIN CONFIGURATION
PIN
Number
Front side
Pin Name
PIN
Number
Back side
Pin Name
PIN
Number
Front side
Pin Name
PIN
Number
Back side
Pin Name
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
Vss
DQMB0
DQMB1
Vcc
A0
A1
A2
Vss
DQ8
DQ9
DQ10
DQ11
Vcc
DQ12
DQ13
DQ14
DQ15
Vss
NC
NC
CLK0
Vcc
/RAS
/WE
/S0
/S1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
Vss
DQMB4
DQMB5
Vcc
A3
A4
A5
Vss
DQ40
DQ41
DQ42
DQ43
Vcc
DQ44
DQ45
DQ46
DQ47
Vss
NC
NC
CKE0
Vcc
/CAS
CKE1
NC
NC
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
NC
Vss
NC
NC
Vcc
DQ16
DQ17
DQ18
DQ19
Vss
DQ20
DQ21
DQ22
DQ23
Vcc
A6
A8
Vss
A9
A10
Vcc
DQMB2
DQMB3
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
SDA
Vcc
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
CLK1
Vss
NC
NC
Vcc
DQ48
DQ49
DQ50
DQ51
Vss
DQ52
DQ53
DQ54
DQ55
Vcc
A7
BA0
Vss
BA1
A11
Vcc
DQMB6
DQMB7
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
SCL
Vcc
NC = No Connection
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ELECTRIC
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22.Sep.2000
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Block Diagram
/S0
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQML /CS
DQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQML /CS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1 D0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1 D2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DQMU
DQMU
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
10Ω
DQML /CS
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D0 - D3
D0 - D3
D0 - D3
D0 - D3
D0 - D3
D0 - D3
SCL
D0 - D3
CLK1
DQML /CS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1 D1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1 D3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DQMU
DQMU
CLK0
CKE0
/RAS
/CAS
/WE
BA0,BA1,A<11:0>
Vcc
Vss
SERIAL PD
A0
A1
A2
SDA
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ELECTRIC
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22.Sep.2000
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table I
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Function described
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
... Data Width continuation
Voltage interface standard of this assembly
SDRAM Cycletime at Max.Supported CAS Latency (CL).
-6,-6L
-7,-7L,-8,-8L
-6,-6L
-7,-7L,-8,-8L
SPD enrty data
128
256 Bytes
SDRAM
A0-A11
A0-A8
1BANK
x64
0
LVTTL
7.5ns
10ns
5.4ns
6ns
Non-PARITY
SPD DATA(hex)
80
08
04
0C
09
01
40
00
01
75
A0
54
60
00
80
10
00
01
8F
04
06
01
01
00
0E
A0
D0
60
70
00
00
17
14
0F
14
17
14
2D
32
Cycle time for CL=3
SDRAM Access from Clock
tAC for CL=3
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
SDRAM width,Primary DRAM
Error Checking SDRAM data width
self refresh(15.625uS)
x16
N/A
1
1/2/4/8/Full page
4bank
2/3
0
0
non-buffered,non-registered
Precharge All,Auto precharge
-6,-6L,-7,-7L
-8,-8L
-6,-6L,-7,-7L
-8,-8L
Minimum Clock Delay,Back to Back Random Column Addresses
Burst Lengths Supported
# Banks on Each SDRAM device
CAS# Latency
CS# Latency
Write Latency
SDRAM Module Attributes
SDRAM Device Attributes:General
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
SDRAM Access form Clock(2nd highest CAS latency)
10ns
13ns
6ns
7ns
N/A
N/A
22.5ns
20ns
15ns
20ns
22.5ns
20ns
45ns
50ns
tAC for CL=2
SDRAM Cycle time(3rd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
-6,-6L
Precharge to Active Minimum
Row Active to Row Active Min.
RAS to CAS Delay Min
Active to Precharge Min
-7,-7L,-8,-8L
-6,-6L
-7,-7L,-8,-8L
-6,-6L
-7,-7L,-8,-8L
-6,-6L
-7,-7L,-8,-8L
MIT-DS-0374-0.3
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ELECTRIC
( 4 / 55 )
22.Sep.2000
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table II
31
Density of each bank on module
Command and Address signal input setup time
-6,-6L
-7,-7L,-8,-8L
64MByte
1.5ns
2ns
0.8ns
1ns
1.5ns
2ns
0.8ns
1ns
option
rev 1.2B
Check sum for -6,-6L
10
15
20
08
10
15
20
08
10
00
12
AC
0D
4D
1CFFFFFFFFFFFFFF
01
02
03
04
4D4838533634415146432D36202020202020
4D4838533634415146432D364C2020202020
4D4838533634415146432D37202020202020
4D4838533634415146432D374C2020202020
4D4838533634415146432D38202020202020
4D4838533634415146432D384C2020202020
32
33
Command and Address signal input hold time
-6,-6L
-7,-7L,-8,-8L
34
-6,-6L
Data signal input setup time
-7,-7L,-8,-8L
-6,-6L
35
36-61
62
Data signal input hold time
-7,-7L,-8,-8L
Superset Information (may be used in future)
SPD Revision
63
64-71
Checksum for bytes 0-62
Manufactures Jedec ID code per JEP-108E
Check sum for -7,-7L
Check sum for -8,-8L
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
Germany
MH8S64AQFC-6
MH8S64AQFC-6L
72
Manufacturing location
73-90
Manufactures Part Number
MH8S64AQFC-7
MH8S64AQFC-7L
MH8S64AQFC-8
MH8S64AQFC-8L
91-92
93-94
95-98
99-125
126
127
128+
Revision Code
Manufacturing date
Assembly Serial Number
Manufacture Specific Data
Intetl specification frequency
Intel specification CAS# Latency support
Unused storage locations
-6,-6L,-7,7L
-8,8L
PCB revision
year/week code
serial number
option
100MHz
CL=2/3,AP,CK0,1
CL=3,AP,CK0,1
open
rrrr
yyww
ssssssss
00
64
8F
8D
00
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