®
ST-BUS™ FAMILY
MH89790B
CEPT PCM 30/CRC-4 Framer & Interface
Preliminary Information
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Complete primary rate 2048 kbit/s CEPT
transceiver with CRC-4 option
Selectable HDB3 or AMI line code
Two frame elastic buffer with 32µs jitter buffer
Tx and Rx frame and multiframe
synchroniza-tion signals
Frame alignment and CRC error counters
Insertion and detection of A, B, C, D signalling
bits with optional debounce
Line driver and receiver
Per channel, overall, and remote loop around
Digital phase detector between E1 line and
ST-BUS
ST-BUS compatible
Pin compatible with the MH89790
Inductorless clock recovery
Loss of Signal (LOS) indication
Available in standard, narrow and surface
mount formats
Supports single supply rail operation
MH89790B
MH89790BN
MH89790BS
ISSUE 5
May 1995
Ordering Information
40 Pin DIL Hybrid 1.3” row pitch
40 Pin DIL Hybrid 0.8“ row pitch
40 Pin Surface Mount Hybrid
0°C to 70°C
Description
The MH89790B is Mitel’s CEPT PCM 30 interface
solution, designed to meet the latest CCITT
standards PCM 30 format with CRC-4.
The
MH89790B provides a complete interface between a
2.048 Mbit/sec digital trunk and Mitel’s
Serial
Telecom Bus, the ST-BUS.
The MH89790B is a pin-compatible enhancement of
the MH89790, permitting the removal of the tuneable
inductor and inclusion of the external NAND gate
used for generating RxD.
Applications
•
•
•
Primary rate ISDN network nodes
Multiplexing equipment
Private network: PBX to PBX links
TxMF
C2i
F0i
RxMF
DSTo
DSTi
CSTi0
CSTi1
CSTo
ST-BUS
Timing
Cicuitry
Digital
Attenu-
ator
ROM
2 Frame
Elastic
Buffer
with Slip
Control
PADi
TxG
PADo
CEPT
Link
Interface
Transmitter
OUTA
OUTB
RxA
RxT
Receiver
LOS
RxR
RxB
Data
Interface
•
•
Serial
Control
Interface
ABCD
Signalling RAM
Control
Logic
Phase
Detector
•
Clock
Extractor
CEPT
Counter
•
E2o
VDD
ADl
XCtl
XSt
•
E8Ko
VSS
Figure 1 - Functional Block Diagram
4-187
MH89790B
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
LOS
NC
NC
NC
NC
VSS
NC
DSTo
NC
OUTB
NC
RxMF
TxMF
OUTA
PADo
TxG
PADi
VSS
Preliminary Information
IC
E2o
VDD
RxA
RxT
RxR
RxB
NC
CSTi1
CSTi0
E8Ko
XCtl
XSt
CSTo
ADl
DSTi
C2i
E2o
F0i
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Figure 2 - Pin Connections
Pin Description
Pin #
2
3
4
5
6
7
Name
IC
E2o
V
DD
RxA
RxT
RxR
Description
Internal Connection.
Leave open circuit.
2048 kHz Extracted Clock (Output):
This clock is extracted by the device from the
received signal. It is used internally to clock in data received at RxT and RxR.
D.C. Power Input. (+5V).
Receive A (Output):
The bipolar CEPT signal received by the device at the RxR and
RxT inputs is converted to a unipolar format and output at this pin.
Receive Tip and Receive Ring Inputs.
The AMI receive signal is input to these pins.
Both inputs should be connected to a center-tapped, center-grounded transformer.If the
receive side of the device is not used, these pins must be tied to ground through 1kΩ
resistors.
Receive B (Output):
The bipolar CEPT signal received by the device at the RxR and
RxT inputs is converted to a unipolar format and output at this pin.
No Connection.
Control ST-BUS Input #1:
A 2048 kbit/s stream that contains channel associated
signalling, frame alignment and diagnostic functions.
Control ST-BUS Input #0:
A 2048 kbit/s stream that contains 30 per channel control
words and two Master Control Words.
8 kHz Extracted Clock (Output):
An 8 kHz output generated by dividing the extracted
2048 kHz clock by 256 and aligning it with the received CEPT frame. The 8 kHz signal
can be used for synchronizing the system clock to the extracted 2048 kHz clock. Only
valid when device achieves synchronization (goes low during a loss of signal or a loss
of basic frame synchronization condition).
E8Ko goes to high impedance when 8kHzSEL = 0 in MCW2.
External Control (Output):
An uncommitted external output pin which is set or reset via
bit 1 in Master Control Word 2 on CSTi0. The state of XCtl is updated once per frame.
External Status:
The state of this pin is sampled once per frame and the status is
reported in bit 1 of the Master Status Word 1 on CSTo.
Control ST-BUS Output:
A 2048 kbit/s serial control stream which provides the 16
signalling words, two Master Status Words, Phase Status Word and CRC Error Count.
8
9
10
11
12
RxB
NC
CSTi1
CSTi0
E8Ko
13
14
15
XCtl
XSt
CSTo
4-188
Preliminary Information
Pin Description (Continued)
Pin #
16
Name
ADI
Description
MH89790B
Alternate Digit Inversion (Input):
If this input is high, the CEPT timeslots which are
specified on CSTi0 as voice channels are ADI coded and decoded. When this bit is low
it disables ADI coding for all channels. This feature allows either ADI or non-ADI codecs
to be used on DSTi and DSTo. Internally pulled with a 4.7kΩ resistor to +V
DD
.
Data ST-BUS Input:
This pin accepts a 2048 kbit/s serial stream which contains the 30
PCM or data channels to be transmitted on the CEPT trunk.
2048 kbit/s System Clock (Input):
The master clock for the ST-BUS section of the
chip. All data on the ST-BUS is clocked in on the falling edge of the C2i and output on the
rising edge. The falling edge of C2i is also used to clock out data on the CEPT PCM 30
transmit link.
2048 kHz Extracted Clock (Output):
Internally connected to pin 3.
Frame Pulse Input:
The ST-BUS frame synchronization signal which defines the
beginning of the 32 channel frame.
Ground.
D.C. Power Return.
PAD Input:
Input to the symmetrical resistive 75 ohm T-type line matching circuit. In a
typical application connect this input to the output of the line driving transformer.
Transmit Ground:
Common point of the T-type PAD circuit. Connect to GND in a typical
application.
PAD Output:
Output from the T-type PAD circuit. Output impedance of the PAD is pure
resistive 75Ω.
Output A (Open Collector Output):
This is the output of the CEPT transmitter. It is
suitable for use with an external pulse transformer to generate the transmit bipolar line
signal.
Transmit Multiframe Boundary (Input):
This input can be used to set the channel
associated and CRC transmitted multiframe boundary (clear the frame counters). If a
transmit multiframe signal is not being generated externally to the device, the MH89790B
will internally generate its own multiframe when this pin is tied high.
Received Multiframe Boundary (Output):
An output pulse delimiting the received
multiframe boundary. (This multiframe is not related to the received CRC multiframe.)
No Connection.
Output B (Open Collector Output):
Output of the CEPT transmitter. It is suitable for
use with an external pulse transformer to generate the transmit bipolar line signal.
No Connection.
Data ST-BUS Output:
A 2048 kbit/s serial output stream which contains the 30 PCM or
data channels received from the CEPT line.
No Connection.
Ground.
D.C. Power Return.
No Connection.
Loss of Signal (Output):
This pin goes High when 128 contiguous ZEROs are received
on the RxT and RxR inputs. When LOS is High, RxA and RxB are forced High. LOS is
reset when 64 ONEs are received in a two E1-frame period.
No Connection.
17
18
DSTi
C2i
19
20
21
22
23
24
25
E2o
F0i
V
SS
PADi
TxG
PADo
OUTA
26
TxMF
27
28
29
30
31
32
33
34 - 37
38
RxMF
NC
OUTB
NC
DSTo
NC
V
SS
NC
LOS
39 - 40
NC
4-189
MH89790B
Functional Description
The MH89790B is a digital trunk interface
conforming to CCITT Recommendation G.704 for
PCM 30 and I.431 for ISDN. It includes features
such as insertion and detection of synchronization
patterns, optional cyclical redundancy check
(CRC-4) and far end error performance reporting,
HDB3 decoding and
optional coding, channel
associated
or
common
channel
signalling,
programmable digital attenuation, and a two frame
received elastic buffer. The MH89790B can also
monitor several conditions on the CEPT digital trunk
which include the following: Loss of Signal (LOS)
indication, frame and multiframe synchronization,
received all 1’s alarms, data slips, as well as near
and far end framing and CRC errors.
The system interface to the MH89790B is a serial
bus that operates at 2048 kbit/s known as the
ST-BUS. This serial stream is divided into 125 µs
frames that are made up of 32 x 8 bit channels.
The line interface to the MH89790B consists of split
phase unipolar inputs and outputs which are
supplied from/to a bipolar line receiver/driver,
respectively.
Preliminary Information
mode. This allows use of timeslot 16 for 64 kbit/s
common channel signalling.
Synchronization is
included within the CEPT bit stream in the form of a
bit pattern inserted into timeslot 0. The contents of
timeslot 0 alternate between the frame alignment
pattern and the non-frame alignment pattern as
described in Figure 3 below. Bit 1 of the frame
alignment and non-frame alignment bytes have
provisions for additional protection against false
synchronization or enhanced error monitoring. This
is described in more detail in the following section.
In order to accomplish multiframe synchronization, a
16 frame multiframe is defined by sending four zeros
in the high order quartet of timeslot 16 frame 0, i.e.,
once every 16 frames (see Figure 4). The CEPT
format has four signalling bits, A, B, C and D.
Signalling bits for all 30 information channels are
transmitted in timeslot 16 of frames 1 to 15. These
timeslots are subdivided into two quartets (see Table
6).
Cyclic Redundancy Check (CRC)
An optional cyclic redundancy check (CRC) has
been incorporated within CEPT bit stream to provide
additional protection against simulation of the frame
alignment signal, and/or where there is a need for an
enhanced error monitoring capability. The CRC
process treats the binary string of ones and zeros
contained in a submultiframe (with CRC bits set to
binary zero) as a single long binary number. This
string of data is first multiplied by x
4
then divided by
the polynomial x
4
+x+1. This process takes place at
both the transmitter and receiver end of the link. The
remainder calculated at the receiver is compared to
the one received with the data over the link. If they
Bit Number
1
2
0
CEPT Interface
The CEPT frame format consists of 32, 8 bit
timeslots. Of the 32 timeslots in a frame, 30 are
defined as information channels, timeslots 1-15 and
17-31 which correspond to telephone channels 1-30.
An additional data channel may be obtained by
placing the device in common channel signalling
3
0
4
1
5
1
6
0
7
1
8
1
Timeslot 0 containing the
frame alignment signal
Timeslot 0 containing the
non-frame alignment signal
Reserved for
International
use
(1)
Reserved for
International
use
(2)
1
Alarm indication to the
remote PCM multiplex
equipment
See
Note
#3
See
Note
#3
See
Note
#3
See
Note
#3
See
Note
#3
Figure 3 - Allocation of Bits in Timeslot 0 of the CEPT Link
Note 1 : With CRC active, this bit is ignored.
Note 2 : With SiMUX active, this bit transmits SMF CRC results in frames 13 and 15.
Note 3 : Reserved for National use.
.
Timeslot 16 of frame 0
Timeslot 16 of frame 1
ABCD bits for
telephone
channel 1
(timeslot 1)
ABCD bits for
telephone
channel 16
(timeslot 17)
Timeslot 16 of frame 15
•••
0000
XYXX
ABCD bits for
telephone
channel 15
(timeslot 15)
ABCD bits for
telephone
channel 30
(timeslot 31)
Figure 4 - Allocation of Bits in Timeslot 16 of the CEPT Link
4-190
Preliminary Information
are the same, it is of high probability that the
previous submultiframe was received error free.
The CRC procedure is based on a 16 frame
multiframe which is divided into two 8 frame
submultiframes (SMF). The frames which contain
the frame alignment pattern contain the CRC bits, C
1
to C
4,
respectively, in the bit 1 position. The frame
which contains the non-frame alignment pattern
contains within the bit 1 position, a 6 bit CRC
multiframe alignment signal and two spare bits (in
frames 13 and 15) which are used for CRC error
performance reporting (refer to Figure 5). During the
CRC encoding procedure the CRC bit positions are
initially set at zero. The remainder of the calculation
is stored and inserted into the respective CRC bits of
the next SMF. The decoding process repeats the
multiplication/division process and compares the
remainder with the CRC bits received in the next
SMF.
The two spare bits (denoted Si1 and Si2 in Figure 5)
following the 6-bit CRC multiframe alignment signal
can be used to monitor far-end error performance.
The results of the CRC-4 comparisons for the
previously received SMFII and SMFI are encoded
and transmitted back to the far end in the Si bits
(refer to Table 1).
MH89790B
ST-BUS Interface
The ST-BUS is a synchronous time division
multiplexed serial bus with data streams operating at
2048 kbit/s and configured as 32, 64 kbit/s channels
(refer Figure 6). Synchronization of the data transfer
is provided from a frame pulse which identifies the
frame boundaries and repeats at an 8 kHz rate.
Figure 2 shows how the
frame pulse (F0i)
defines the ST-BUS frame boundaries. All data is
clocked into the device on the falling edge of the
2048 kbit/s clock (C2i), while data is clocked out on
the rising edge of the 2048 kbit/s clock at the start of
the bit cell.
Si1 bit
(frame
13)
1
1
0
0
Si2 bit
(frame
15)
1
0
1
0
Meaning
CRC results for both SMFI, II are
error free.
CRC result for SMFII is in error.
CRC result for SMFI is error free.
CRC result for SMFII is error free.
CRC result for SMFI is in error.
CRC results for both SMFI, II are
in error.
Table 1. Coding of Spare Bits Si1 and Si2
Multiple Frame
Component
Frame Type
Frame Alignment Signal
Non-Frame Alignment Signal
CRC
Frame #
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Timeslot Zero
1
C
1
0
C
2
0
C
3
1
C
4
0
C
1
1
C
2
1
C
3
Si1
(3)
2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3
0
A
(1)
0
A
(1)
0
A
(1)
0
A
(1)
0
A
(1)
0
A
(1)
0
A
(1)
0
A
(1)
4
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
5
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
6
0
Sn
(2)
0
Sn
(2)
0
Sn
(2)
0
Sn
(2)
0
Sn
(2)
0
Sn
(2)
0
Sn
(2)
0
Sn
(2)
7
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
8
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
S
M
F
I
Frame Alignment Signal
Non-Frame Alignment Signal
Frame Alignment Signal
Non-Frame Alignment Signal
Frame Alignment Signal
Non-Frame Alignment Signal
Frame Alignment Signal
S
M
F
I
I
Non-Frame Alignment Signal
Frame Alignment Signal
Non-Frame Alignment Signal
Frame Alignment Signal
Non-Frame Alignment Signal
Frame Alignment Signal
Non-Frame Alignment Signal
C
4
Si2
(3)
Figure 5 - CRC Bit Allocation and Submultiframing
Note 1 : Remote Alarm. Keep at 0 for normal operation.
Note 2 : Reserved for National use. Keep at 1 for normal operation.
Note 3 : Used to monitor far-end CRC error performance.
indicates position of CRC-4 multiframe alignment signal
4-191
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