MITSUBISHI LSIs
MH4M36CJD-5,-6,-7
FAST PAGE MODE ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
DESCRIPTION
The MH4M36CJD is an 4M word by 36-bit dynamic
RAM module and consists of 8 industry standard
4M X 4 dynamic RAMs in TSOP and 4 industry
standard 4M X 1 dynamic RAMs in TSOP.
The ICs are mounted on both sides of small
ceracom PC boards and form a convenient 64-pin
WDIP package.
PIN CONFIGURATION ( TOP VIEW )
FEATURES
Type name
RAS
CAS
access access
time
time
(max.ns) (max.ns)
Address
OE
Cycle
Power
access
access
dissipa-
time
time
time
tion
(max.ns) (max.ns) (min.ns) (typ.mW)
MH4M36CJD-5
MH4M36CJD-6
MH4M36CJD-7
50
60
70
13
15
20
25
30
35
13
15
20
90
110
130
7240
5920
5200
Utilizes industry standard 4M X 4 DRAMs in TSOP package
and 4M X 1 DRAMs in TSOP package
Single 5V ± 10%supply
Low stand-by power dissipation
66mW (Max) . . . . . . . . . . . . . . . . . . . CMOS lnput level
Low operating power dissipation
MH4M36CJD - 5 . . . . . . . . . . . . . . . . . 9.15W (Max)
MH4M36CJD - 6 . . . . . . . . . . . . . . . . . 7.48W (Max)
MH4M36CJD - 7 . . . . . . . . . . . . . . . . . 6.51W (Max)
All inputs, output TTL compatible and low capacitance
2048 refresh cycles every 32ms (A
0
~ A
10
)
Includes 12 0.22uF decoupling capacitors
APPLICATION
Main memory unit for computers, Microcomputer memory,
Refresh memory for CRT
DQ0 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
DQ5 6
Vss 7
DQ6 8
DQ7 9
DQP0 10
/CAS0 11
DQ8 12
DQ9 13
Vcc 14
DQ10 15
DQ11 16
DQ12 17
DQ13 18
DQ14 19
DQ15 20
Vss 21
DQP1 22
/CAS1 23
A0 24
A1 25
A2 26
A3 27
Vcc
A4
A5
A6
A7
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
DQ21
DQ22
DQ23
DQP2
/CAS2
Vss
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
Vcc
DQ30
DQ31
DQP3
/CAS3
/RAS0
RFU
Vss
/W
RFU
RFU
A10
A9
A8
MIT-DS-0035-0.0
MITSUBISHI
ELECTRIC
( 1 / 14 )
Jun/17/1996
MITSUBISHI LSIs
MH4M36CJD-5,-6,-7
FAST PAGE MODE ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
FUNCTION
The MH4M36CJD provide, in addition
to normal read and write a number of other functions,
e.g., fast page mode, RAS-only refresh.
The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Inputs
Operation
RAS
Read
Write (Early write)
RAS-only refresh
Hidden refresh
CAS before RAS refresh
Standby
ACT
ACT
ACT
ACT
ACT
NAC
CAS
ACT
ACT
NAC
ACT
ACT
DNC
W
NAC
ACT
DNC
DNC
NAC
DNC
OE
ACT
DNC
DNC
ACT
DNC
DNC
Row
address
APD
APD
APD
DNC
DNC
DNC
Column
address
APD
APD
DNC
DNC
DNC
DNC
Input/Output
Refresh
Input
OPN
APD
DNC
OPN
DNC
DNC
Output
VLD
OPN
OPN
VLD
OPN
OPN
YES
YES
YES
YES
YES
NO
Fast page
mode
identical
Remark
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid,APD : applied, OPN : open
BLOCK DIAGRAM
Add
38
/W
41
/RAS0
11
/CAS0
24,25,26,27,29,30,31,32,33,34,35
54
/CAS2
CAS RAS WE Add OE
M5M417400CTP
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
1
2
3
4
5
6
8
9
CAS RAS WE Add OE
M5M417400CTP
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
64
63
62
61
59
58
57
56
CAS RAS WE Add OE
CAS RAS WE Add OE
M5M417400CTP
M5M417400CTP
CAS RAS WE Add OE
CAS RAS WE Add OE
M5M44100CTP
DQP0
10
M5M44100CTP
DQP2
55
23
/CAS1
CAS RAS WE Add OE
42
/CAS3
M5M417400CTP
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
12
13
15
16
17
18
19
20
CAS RAS WE Add OE
M5M417400CTP
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
52
51
50
49
48
47
45
44
CAS RAS WE Add OE
CAS RAS WE Add OE
M5M417400CTP
M5M417400CTP
CAS RAS WE Add OE
CAS RAS WE Add OE
M5M44100CTP
DQP1
22
M5M44100CTP
DQP3
43
MIT-DS-0035-0.0
MITSUBISHI
ELECTRIC
( 2 / 14 )
Jun/17/1996
MITSUBISHI LSIs
MH4M36CJD-5,-6,-7
FAST PAGE MODE ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
VI
V0
I0
Pd
Topr
Tstg
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
Ta=25 C
With respect to Vss
Parameter
Conditions
Ratings
-1 ~ 7
-1 ~ 7
-1 ~ 7
50
12
0 ~ 70
-40 ~ 125
(Ta=0 ~ 70 °C, unless otherwise noted)
(Note 1)
Limits
Min
4.5
0
2.4
-1.0
Nom
5
0
Max
5.5
0
6.0
0.8
Unit
V
V
V
V
Unit
V
V
V
mA
W
C
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Vcc
Vss
V
IH
V
IL
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage, all inputs
Parameter
Note 1 : All voltage values are with respect to Vss
ELECTRICAL CHARACTERISTICS
Symbol
V
OH
V
OL
I
OZ
I
I
Parameter
High-level output voltage
Low-level output voltage
Off-state output current
Input current
Average supply current
from Vcc
operating
(Note 3,4)
I
CC2
(Ta=0 ~ 70 °C, Vcc=5V ± 10%, Vss=0V, unless otherwise noted)
(Note 2)
Test conditions
I
OH
=-5mA
I
OL
=4.2mA
Q floating 0V
≤
V
OUT
≤
5.5V
0V
≤
V
IN
≤
6.0V, Other inputs pins=0V
Limits
Min
2.4
0
-10
-120
Typ
Max
Vcc
0.4
10
120
1660
1360
1180
RAS= CAS =V
IH,
output open
RAS= CAS
≥
Vcc -0.5
RAS cycling, CAS= V
IH
t
RC
=min.
output open
24
12
1660
1360
1180
1060
900
780
1580
CAS before RAS refresh cycling
t
RC
=min.
output open
1300
1140
mA
mA
mA
mA
mA
Unit
V
V
uA
uA
MH4M36CJD-5
MH4M36CJD-6
MH4M36CJD-7
I
CC1 (AV)
RAS, CAS cycling
t
RC
=t
WC
=min.
output open
Supply current from Vcc , stand-by
Average supply current
from Vcc
refreshing
(Note 3)
Average supply current
from Vcc
Fast-Page-Mode
(Note 3,4)
Average supply current
from Vcc
CAS before RAS refresh
(Note 3)
mode
MH4M36CJD-5
MH4M36CJD-6
MH4M36CJD-7
MH4M36CJD-5
MH4M36CJD-6
MH4M36CJD-7
MH4M36CJD-5
MH4M36CJD-6
MH4M36CJD-7
I
CC3 (AV)
I
CC4(AV)
RAS=V
IL,
CAS cycling
t
PC
=min.
output open
I
CC6(AV)
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc3 (AV) , Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
CAPACITANCE
Symbol
C
I (A)
C
I (W)
C
I (RAS)
C
I (CAS)
C
I / O
(Ta=0 ~ 70 °C , Vcc=5V ± 10%, Vss=0V, unless otherwise noted)
Limits
Min
Typ
Max
90
130
130
35
20
Parameter
Input capacitance, address inputs
Input capacitance, write control input
Input capacitance, RAS input
Input capacitance, CAS input
Input/Output capacitance, data ports
V
I
=Vss
Test conditions
Unit
pF
pF
pF
pF
pF
f=1MH
Z
Vi=25mVrms
MIT-DS-0035-0.0
MITSUBISHI
ELECTRIC
( 3 / 14 )
Jun/17/1996
MITSUBISHI LSIs
MH4M36CJD-5,-6,-7
FAST PAGE MODE ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70 °C, Vcc=5V ± 10%, Vss=0V, unless otherwise noted , see notes 5,12,13)
Limits
Symbol
t
CAC
t
RAC
t
AA
t
CPA
t
CLZ
t
OFF
Parameter
Access time from CAS
Access time from RAS
Columu address access time
Access time from CAS precharge
Output disable time after CAS high
(Note 6,7)
(Note 6,8)
(Note 6,9)
(Note 6,10)
5
0
13
(Note 11)
MH4M36CJD-5
Min
Max
13
50
25
30
5
0
15
MH4M36CJD-6
Min
Max
15
60
30
35
5
0
15
MH4M36CJD-7
Min
Max
20
70
35
40
ns
ns
ns
ns
ns
ns
Unit
Output low impedance time from CAS low (Note 6)
Note 5: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing a RAS clock such as RAS-Only refresh).
Note the RAS may be cycled during the initial pause . And any 8 RAS or RAS/CAS cycles are required after prolonged periods
(greater than 32 ms) of RAS inactivity before proper device operation is achieved.
6: Measured with a load circuit equivalent to 2TTL loads and 100pF.
7: Assumes that tRCD
≥
tRCD(max) and tASC
≥
tASC(max).
8: Assumes that tRCD
≤
tRCD(max) and tRAD
≤
tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,
tRAC will increase by amount that tRCD exceeds the value shown.
9: Assumes that tRAD
≥
tRAD(max) and tASC
≤
tASC(max).
10: Assumes that tCP
≤
tCP(max) and tASC
≥
tASC(max).
11: tOFF(max) and tOEZ (max) defines the time at which the output achieves the high impedance state ( | IOUT |
≤
10 uA) and is not reference to
VOH(min) or VOL(max).
TIMING REQUIREMENTS (For Read, Write,Refresh, and Fast-Page Mode Cycles)
(Ta=0 ~ 70 °C, Vcc=5V ± 10%, Vss=0V, unless otherwise noted See notes 12,13)
Limits
Symbol
t
REF
t
RP
t
RCD
t
CRP
t
RPC
t
CPN
t
RAD
t
ASR
t
ASC
t
RAH
t
CAH
t
DZC
t
CDD
t
T
Refresh cycle time
RAS high pulse width
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
Parameter
MH4M36CJD-5
Min
30
(Note14)
18
10
0
10
(Note15)
(Note16)
13
0
0
8
13
(Note17)
(Note18)
(Note19)
0
13
1
50
10
25
37
Max
32
MH4M36CJD-6
Min
40
20
10
0
10
15
0
0
10
15
0
15
1
50
10
30
45
Max
32
MH4M36CJD-7
Min
50
20
10
0
10
15
0
0
10
15
0
15
1
50
10
35
50
Max
32
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to CAS low
Delay time, CAS high to data
Transition time
Note 12: The timing requirements are assumed tT =5ns.
13: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
14: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access
time is controlled exclusively by tCAC or tAA. tRCD(min) is specified as tRCD(min) =tRAH(min) +2tH+tASC(min).
15: tRAD(max) is specified as a reference point only. If tRAD
≥
tRAD(max) and tASC
≤
tASC(max), access time is controlled exclusively by tAA.
16: tASC(max) is specified as a reference point only. If tRCD
≥
tRCD(max) and tASC
≥
tASC(max), access time is controlled exclusively by tCAC.
17: Either tDZC or tDZO must be satisfied.
18: Either tCDD or tODD must be satisfied.
19: tT is measured between VIH(min) and VIL(max).
MIT-DS-0035-0.0
MITSUBISHI
ELECTRIC
( 4 / 14 )
Jun/17/1996
MITSUBISHI LSIs
MH4M36CJD-5,-6,-7
FAST PAGE MODE ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
Read and Refresh Cycles
Limits
Symbol
t
RC
t
RAS
t
CAS
t
CSH
t
RSH
t
RCS
t
RCH
t
RRH
t
RAL
Read cycle time
RAS iow pulse width
CAS iow pulse width
CAS hold time after RAS iow
RAS hold time after CAS iow
Read Setup time after CAS high
Read hold time after CAS iow
Read hold time after RAS iow
Column address to RAS hold time
(Note 20)
(Note 20)
Parameter
MH4M36CJD-5
Min
90
50
13
50
13
0
0
10
25
Max
10000
10000
MH4M36CJD-6
Min
110
60
15
60
15
0
0
10
30
Max
10000
10000
MH4M36CJD-7
Min
130
70
20
70
20
0
0
10
35
Max
ns
10000
10000
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Note 20: Either t
RCH
or t
RRH
must be satisfied for a read cycle.
Write Cycle
Limits
Symbol
t
WC
t
RAS
t
CAS
t
CSH
t
RSH
t
WCS
t
WCH
t
CWL
t
RWL
t
WP
t
DS
t
DH
Write cycle time
RAS iow pulse width
CAS iow pulse width
CAS hold time after RAS iow
RAS hold time after CAS iow
Write setup time before CAS low
Write hold time after CAS iow
CAS hold time after W iow
RAS hold time after W iow
Write pulse width
Data setup time before CAS iow or W iow
Data hold time after CAS iow or W iow
Parameter
MH4M36CJD-5
Min
90
50
13
50
13
0
8
13
13
8
0
8
10000
10000
Max
MH4M36CJD-6
Min
110
60
15
60
15
0
10
15
15
10
0
10
10000
10000
Max
MH4M36CJD-7
Min
130
70
20
70
20
0
15
20
20
15
0
15
10000
10000
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
MIT-DS-0035-0.0
MITSUBISHI
ELECTRIC
( 5 / 14 )
Jun/17/1996
NXP MCU
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