MH1S72CPG-12 datasheet, PDF - EEWORLD Datasheet

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MH1S72CPG-12: Description75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM; Categorystorage storage; File Size437KB，47 Pages; ManufacturerMitsubishi; Websitehttp://www.mitsubishielectric.com/semiconductors/

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MH1S72CPG-12 Overview

75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM

MH1S72CPG-12 Parametric

Parameter Name	Attribute value
Maker	Mitsubishi
Parts packaging code	DIMM
package instruction	,
Contacts	168
Reach Compliance Code	unknow
ECCN code	EAR99
JESD-30 code	R-XDMA-N168
memory density	75497472 bi
Memory IC Type	SYNCHRONOUS DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	168
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
organize	1MX72
Package body material	UNSPECIFIED
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Terminal form	NO LEAD
Terminal location	DUAL

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Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH1S72CPG-10,-12,-15

75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM

DESCRIPTION

The MH1S72CPG is 1048576-word by 64-bit

Synchronous DRAM module. This consists of five

industry standard 1Mx16 Synchronous DRAMs in

TSOP and one industory standard EEPROM in

TSSOP.

The mounting of TSOP on a card edge Dual Inline

package provides any application where high

densities and large quantities of memory are

required.

This is a socket type - memory modules, suitable for

easy interchange or addition of modules.

85pin

1pin

FEATURES

Frequency

-10

-12

-15

100MHz

83MHz

67MHz

CLK Access Time

(Component SDRAM)

94pin

95pin

10pin

11pin

8ns(CL=3)

8ns (CL=3)

Back side

9ns (CL=3)

Front side

Utilizes industry standard 1M x 16 Synchronous DRAMs

TSOP and industry standard EEPROM in TSSOP

168-pin (84-pin dual in-line package)

124pin

125pin

40pin

41pin

single 3.3V±0.3V power supply

Clock frequency 100MHz/83MHz/67MHz

Fully synchronous operation referenced to clock rising

edge

Dual bank operation controlled by BA(Bank Address)

/CAS latency- 1/2/3(programmable)

Burst length- 1/2/4/8(programmable)

Burst type- sequential / interleave(programmable)

Column access - random

Auto precharge / All bank precharge controlled by A10

Auto refresh and Self refresh

4096 refresh cycle /64ms

LVTTL Interface

168pin

84pin

APPLICATION

main memory or graphic memory in computer systems

Module item "-10","-12" , and "-15" show mounted SDRAM devices Cycle time(min.).

MIT-DS-0089-3.0

MITSUBISHI

ELECTRIC

( 1 / 47 )

28.Mar.1997

MH1S72CPG-12 Related Products

	MH1S72CPG-12	MH1S72CPG-15	MH1S72CPG-10
Description	75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM	75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM	75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
Maker	Mitsubishi	Mitsubishi	-
Parts packaging code	DIMM	DIMM	-
Contacts	168	168	-
Reach Compliance Code	unknow	unknow	-
ECCN code	EAR99	EAR99	-
JESD-30 code	R-XDMA-N168	R-XDMA-N168	-
memory density	75497472 bi	75497472 bi	-
Memory IC Type	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	-
memory width	72	72	-
Number of functions	1	1	-
Number of ports	1	1	-
Number of terminals	168	168	-
word count	1048576 words	1048576 words	-
character code	1000000	1000000	-
Operating mode	SYNCHRONOUS	SYNCHRONOUS	-
organize	1MX72	1MX72	-
Package body material	UNSPECIFIED	UNSPECIFIED	-
Package shape	RECTANGULAR	RECTANGULAR	-
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	-
Certification status	Not Qualified	Not Qualified	-
Maximum supply voltage (Vsup)	3.6 V	3.6 V	-
Minimum supply voltage (Vsup)	3 V	3 V	-
Nominal supply voltage (Vsup)	3.3 V	3.3 V	-
surface mount	NO	NO	-
technology	CMOS	CMOS	-
Terminal form	NO LEAD	NO LEAD	-
Terminal location	DUAL	DUAL	-

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